公开(公告)号：US07129168B2

公开(公告)日：2006-10-31

申请号：US10691500

申请日：2003-10-24

申请人： Katsuya Nozawa ,  Tohru Saitoh ,  Teruhito Ohnishi

发明人： Katsuya Nozawa ,  Tohru Saitoh ,  Teruhito Ohnishi

IPC分类号： H01L21/44

CPC分类号： G01K11/02 ,  Y10S438/933

摘要： A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer (103) on a SiGe layer (102) formed on a substrate for temperature estimation (101) constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer (103) and the substrate temperature of the substrate for temperature estimation.

公开(公告)号：US20060126701A1

公开(公告)日：2006-06-15

申请号：US10691500

申请日：2003-10-24

申请人： Katsuya Nozawa ,  Tohru Saitoh ,  Teruhito Ohnishi

发明人： Katsuya Nozawa ,  Tohru Saitoh ,  Teruhito Ohnishi

IPC分类号： G01K13/00

CPC分类号： G01K11/02 ,  Y10S438/933

摘要： A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer (103) on a SiGe layer (102) formed on a substrate for temperature estimation (101) constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer (103) and the substrate temperature of the substrate for temperature estimation.

摘要翻译： 根据本发明的估计衬底温度的方法包括以下步骤：在反应控制下由Si衬底构成的用于温度估计的衬底上形成的SiGe层（102）上外延生长含Si层（103） 条件; 发现含Si层的生长速率与用于温度估计的衬底的衬底温度之间的关系; 在用于器件制造的衬底上外延生长含Si层，作为在反应控制条件下的衬底温度估计的对象; 以及基于后面的含Si层的生长速率和前述含Si层（103）的生长速度与衬底的衬底温度之间的关系，估计用于器件制造的衬底的衬底温度 温度估计。

公开(公告)号：US06919253B2

公开(公告)日：2005-07-19

申请号：US10359553

申请日：2003-02-07

申请人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

发明人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

摘要翻译： 根据本发明的制造半导体器件的方法包括步骤A，其在衬底的表面上形成多晶或无定形初级半导体层以具有开口部分和在同时形成外延生长层的步骤B上 通过开口部分的衬底的暴露部分和初步半导体层上的非外延生长层，使用CVD方法，同时通过反应室内的热源在反应室内加热衬底，外延 生长层由单晶半导体制成，非外延生长层由多晶或非晶半导体层组成。

公开(公告)号：US20050066887A1

公开(公告)日：2005-03-31

申请号：US10359553

申请日：2003-02-07

申请人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

发明人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/739 ,  H01L31/0336

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

摘要翻译： 根据本发明的制造半导体器件的方法包括步骤A，其在衬底的表面上形成多晶或无定形初级半导体层以具有开口部分和在同时形成外延生长层的步骤B上 通过开口部分的衬底的暴露部分和初步半导体层上的非外延生长层，使用CVD方法，同时通过反应室内的热源在反应室内加热衬底，外延 生长层由单晶半导体制成，非外延生长层由多晶或非晶半导体层组成。

公开(公告)号：US5031056A

公开(公告)日：1991-07-09

申请号：US267995

申请日：1988-11-04

申请人： Hitoshi Okada ,  Katsuya Nozawa ,  Shinichiro Terada

发明人： Hitoshi Okada ,  Katsuya Nozawa ,  Shinichiro Terada

IPC分类号： G11B15/43 ,  G11B15/665

CPC分类号： G11B15/43 ,  G11B15/6653

摘要： In a tape player configured to wind a tape pulled out of a cassette onto a rotary head to play the tape, a tension mechanism includes a mode member to control the position of a tension control member according to a selected tape mode so as to establish relative contact between a tension member and a tape under a constant pressure in a play mode and separate them in a stop mode.

摘要翻译： 在被配置为将从磁带拉出的磁带卷绕到旋转磁头上以便播放磁带的磁带机中，张紧机构包括：模制部件，用于根据所选择的磁带模式控制张力控制部件的位置，以便建立相对的 在播放模式下在恒定压力下在张力构件和带之间接触并在停止模式下分离它们。

公开(公告)号：US07105449B1

公开(公告)日：2006-09-12

申请号：US10111599

申请日：2000-10-27

申请人： Katsuya Nozawa ,  Minoru Kubo ,  Tohru Saitoh

发明人： Katsuya Nozawa ,  Minoru Kubo ,  Tohru Saitoh

IPC分类号： H01L21/302

CPC分类号： H01L21/02046 ,  H01L21/31116 ,  H01L21/8249

摘要： A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.

摘要翻译： 进行了湿式清洗的基板的热清洗是在高真空气氛下进行的，以除去留在基板上的氧化膜。 此后，在氢气氛下进行热清洗以除去诸如碳等的污染物。 此时，氧化膜已经被去除，因此通过相对低的温度和短时间的热清洁有效地去除污染。 因此，防止了在衬底上形成的杂质扩散层中的杂质浓度分布的劣化的问题。

公开(公告)号：US06762106B2

公开(公告)日：2004-07-13

申请号：US10326059

申请日：2002-12-23

申请人： Shigetaka Aoki ,  Tohru Saitoh ,  Katsuya Nozawa

发明人： Shigetaka Aoki ,  Tohru Saitoh ,  Katsuya Nozawa

IPC分类号： H01L21331

CPC分类号： H01L29/7378 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

摘要翻译： 包含Si缓冲层，SiGe间隔层，渐变SiGe层和Si覆盖层的Si / SiGe层在对应于集电极开口的区域中外延生长，而多晶层沉积在氮化物膜的上表面上 ，以及氧化膜和氮化物膜的侧表面。 在这种情况下，首先形成Si缓冲层，然后形成诸如SiGe间隔层的其它层，从而确保非选择性外延生长。 然后，在氮化物膜上沉积多晶层。

公开(公告)号：US06713790B2

公开(公告)日：2004-03-30

申请号：US10212799

申请日：2002-08-07

申请人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

发明人： Akira Asai ,  Teruhito Oonishi ,  Takeshi Takagi ,  Tohru Saitoh ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Yo Ichikawa

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/7378

摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.

摘要翻译： 在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。 通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。 在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。 因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

公开(公告)号：US06537369B1

公开(公告)日：2003-03-25

申请号：US09979881

申请日：2001-11-27

申请人： Tohru Saitoh ,  Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Minoru Kubo

发明人： Tohru Saitoh ,  Yoshihiko Kanzawa ,  Katsuya Nozawa ,  Minoru Kubo

IPC分类号： C30B2302

CPC分类号： H01L29/161 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  Y10T428/12674 ,  Y10T428/265

摘要： A B-doped Si1−x−yGexCy layer 102 (where 0

摘要翻译： 使用UHV-CVD工艺在Si衬底101上外延生长B掺杂的Si1-x-yGexCy层102（其中0

公开(公告)号：US06399970B2

公开(公告)日：2002-06-04

申请号：US08931562

申请日：1997-09-16

申请人： Minoru Kubo ,  Katsuya Nozawa ,  Masakatsu Suzuki ,  Takeshi Uenoyama ,  Yasuhito Kumabuchi

发明人： Minoru Kubo ,  Katsuya Nozawa ,  Masakatsu Suzuki ,  Takeshi Uenoyama ,  Yasuhito Kumabuchi

IPC分类号： H01L29778

CPC分类号： H01L29/66431 ,  H01L21/8238 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029 ,  H01L29/161 ,  H01L29/7782

摘要： Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

摘要翻译： Si和SiGeC层形成在Si衬底上的NMOS晶体管中。 使用存在于SiGeC和Si层之间的异质界面处的导带的不连续部分来形成载流子积累层。 电子在作为通道的载流子累积层中行进。 在SiGeC层中，电子迁移率大于硅中的电子迁移率，从而增加NMOS晶体管的工作速度。 在PMOS晶体管中，通过在SiGe和Si层之间的界面处使用价带的不连续部分来形成空穴行进的沟道。 SiGe层中的空穴迁移率也大于Si层，因此增加PMOS晶体管的工作速度。 可以提供具有场效应晶体管的半导体器件，其具有在晶体缺陷中减少的沟道。