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1.发明授权Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability 有权后化学机械抛光蚀刻，以提高时间依赖的介电击穿可靠性公开(公告)号：US08465657B2
公开(公告)日：2013-06-18
申请号：US11833283
申请日：2007-08-03
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewara , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewara , Ping-Chuan Wang , Yun-Yu Wang
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。
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公开(公告)号：US07473636B2
公开(公告)日：2009-01-06
申请号：US11306825
申请日：2006-01-12
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Vincent J. McGahay , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Vincent J. McGahay , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.
摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。
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3.发明授权Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing 失效使用后化学机械抛光形成互连结构或互连和通孔结构的方法公开(公告)号：US07287325B2
公开(公告)日：2007-10-30
申请号：US10908392
申请日：2005-05-10
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01K3/10
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。
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公开(公告)号：US08378447B2
公开(公告)日：2013-02-19
申请号：US13085632
申请日：2011-04-13
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.
摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。
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公开(公告)号：US20120249159A1
公开(公告)日：2012-10-04
申请号：US13074407
申请日：2011-03-29
申请人： Ronald G. Filippi , Griselda Bonilla , Kaushik Chanda , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Ronald G. Filippi , Griselda Bonilla , Kaushik Chanda , Stephan Grunow , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
CPC分类号： H01L23/5226 , G01R31/025 , G01R31/04 , G01R31/07 , G01R31/327 , H01L23/5256 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53295 , H01L23/58 , H01L2924/0002 , H01L2924/00
摘要： A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.
摘要翻译： 线路的后端（BEOL）保险丝结构具有一叠通孔。 通孔的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬里和种子层的弱点导致电迁移（EM）故障的较高概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔丝编程之后受损区域的程度，并防止损坏的介质区域的进一步传播。
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6.发明申请公开(公告)号：US20110175226A1
公开(公告)日：2011-07-21
申请号：US12691213
申请日：2010-01-21
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76816 , H01L21/76846 , H01L21/76847 , H01L23/522 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line
摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分
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公开(公告)号：US07683651B2
公开(公告)日：2010-03-23
申请号：US12348434
申请日：2009-01-05
CPC分类号： G01R31/2858
摘要： A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.
摘要翻译： 公开了用于电迁移的测试结构及相关方法。 测试结构可以包括多个多链测试集的阵列，每个多链测试集包括定位在电介质材料内并以串联配置连接的多个金属线; 每个多链路测试集合以与其他多链路测试集合的并行配置连接，所述并行配置包括到每个多链路测试集合中的第一金属线的阴极端的第一电连接和到第一金属线的阳极端的第二电连接 每条多链测试集中的最后一条金属线。
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8.发明申请SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER 有权半导体接线结构包括金属盖层中的电介质盖公开(公告)号：US20080308942A1
公开(公告)日：2008-12-18
申请号：US11761495
申请日：2007-06-12
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76865 , H01L23/53223 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.
摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。
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公开(公告)号：US07521952B2
公开(公告)日：2009-04-21
申请号：US11830368
申请日：2007-07-30
CPC分类号： G01R31/2858
摘要： A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.
摘要翻译： 公开了用于电迁移的测试结构及相关方法。 测试结构可以包括多个多链测试集的阵列，每个多链测试集包括定位在电介质材料内并以串联配置连接的多个金属线; 每个多链路测试集合以与其他多链路测试集合的并行配置连接，所述并行配置包括到每个多链路测试集合中的第一金属线的阴极端的第一电连接和到第一金属线的阳极端的第二电连接 每条多链测试集中的最后一条金属线。
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10.发明授权Interconnect structure for integrated circuits having enhanced electromigration resistance 有权具有增强的电迁移电阻的集成电路的互连结构公开(公告)号：US08232646B2
公开(公告)日：2012-07-31
申请号：US12691213
申请日：2010-01-21
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76816 , H01L21/76846 , H01L21/76847 , H01L23/522 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.
摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分 。
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