公开(公告)号：US07955514B2

公开(公告)日：2011-06-07

申请号：US11679926

申请日：2007-02-28

申请人： Kazue Takahashi ,  Hitoshi Tamura ,  Motohiro Tanaka ,  Motohiko Yoshigai

发明人： Kazue Takahashi ,  Hitoshi Tamura ,  Motohiro Tanaka ,  Motohiko Yoshigai

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01J37/32477 ,  H01J37/32623 ,  H01J37/32834 ,  H01J37/32862

摘要： A plasma processing apparatus having a processing chamber and a sample base, and processing a sample by using plasma generated inside the processing chamber, the processing chamber being located inside a vacuum container, the sample base being located inside the processing chamber, the sample being mounted on the sample base, the plasma processing apparatus including a component member configuring inner-side wall surface of the processing chamber, and having a dielectric portion on the inner-side wall surface, an exhaustion unit for exhausting the inside of the processing chamber, and an electric-field supply unit for supplying an electric field to the component member in a state where the plasma will not be generated inside the processing chamber, wherein magnitude of the electric field supplied from the electric-field supply unit is changed rapidly while exhausting the inside of the processing chamber by the exhaustion unit.

摘要翻译： 一种等离子体处理装置，其具有处理室和样品基底，并且通过使用在处理室内产生的等离子体处理样品，处理室位于真空容器内，样品基座位于处理室内部，样品被安装 在样品基体上，等离子体处理装置包括构成处理室的内侧壁面的构成部件，在内侧壁面上具有电介质部分，排出处理室内部的排出部，以及 电场供给单元，用于在处理室内不产生等离子体的状态下向构件部件供给电场，其中，从电场供给单元供给的电场的大小迅速变化，同时排出 通过排气单元在处理室内部。

公开(公告)号：US20080169065A1

公开(公告)日：2008-07-17

申请号：US11679926

申请日：2007-02-28

申请人： Kazue Takahashi ,  Hitoshi Tamura ,  Motohiro Tanaka ,  Motohiko Yoshigai

发明人： Kazue Takahashi ,  Hitoshi Tamura ,  Motohiro Tanaka ,  Motohiko Yoshigai

IPC分类号： C23F1/00

CPC分类号： H01J37/32477 ,  H01J37/32623 ,  H01J37/32834 ,  H01J37/32862

摘要： A plasma processing apparatus having a processing chamber and a sample base, and processing a sample by using plasma generated inside the processing chamber, the processing chamber being located inside a vacuum container, the sample base being located inside the processing chamber, the sample being mounted on the sample base, the plasma processing apparatus including a component member configuring inner-side wall surface of the processing chamber, and having a dielectric portion on the inner-side wall surface, an exhaustion unit for exhausting the inside of the processing chamber, and an electric-field supply unit for supplying an electric field to the component member in a state where the plasma will not be generated inside the processing chamber, wherein magnitude of the electric field supplied from the electric-field supply unit is changed rapidly while exhausting the inside of the processing chamber by the exhaustion unit.

摘要翻译： 一种等离子体处理装置，其具有处理室和样品基底，并且通过使用在处理室内产生的等离子体处理样品，处理室位于真空容器内，样品基座位于处理室内部，样品被安装 在样品基底上，等离子体处理装置包括构成处理室的内侧壁面的构成部件，在内侧壁面上具有电介质部分，排出处理室内部的排气单元，以及 电场供给单元，用于在处理室内不产生等离子体的状态下向构件部件供给电场，其中，从电场供给单元供给的电场的大小迅速变化，同时排出 通过排气单元在处理室内部。

公开(公告)号：US06235146B1

公开(公告)日：2001-05-22

申请号：US09313253

申请日：1999-05-18

申请人： Masanori Kadotani ,  Saburo Kanai ,  Youichi Itou ,  Takashi Fujii ,  Hironobu Kawahara ,  Ryouji Hamasaki ,  Kazue Takahashi ,  Motohiko Yoshigai

发明人： Masanori Kadotani ,  Saburo Kanai ,  Youichi Itou ,  Takashi Fujii ,  Hironobu Kawahara ,  Ryouji Hamasaki ,  Kazue Takahashi ,  Motohiko Yoshigai

IPC分类号： H01L2100

CPC分类号： H01L21/67023 ,  H01J2237/2001 ,  Y10S156/914

摘要： A stage with an electrostatic attracting means is adapted for use in a wafer treatment at a high temperature in a vacuum treatment system. In a vacuum treatment system having a stage provided in a treatment chamber, which electrostatically attracts an object to the stage in a low pressure atmosphere, and treats the object at high temperature by heating the stage, an electrode member of the stage is made of titanium or a titanium alloy and a dielectric film for electrostatic attraction is formed on the electrode member. In order to bond firmly titanium and alumina ceramics, it is desirable to sandwich a nickel alloy (Ni—Al) between the materials.

摘要翻译： 具有静电吸引装置的阶段适用于在真空处理系统中在高温下进行晶片处理。 在具有设置在处理室中的阶段的真空处理系统中，其在低压气氛中将物体静电吸引到工作台上，并且通过加热工作台在高温下处理物体，所述工作台的电极构件由钛制成 或者在电极部件上形成钛合金和静电吸引用的电介质膜。 为了牢固地结合钛和氧化铝陶瓷，期望在材料之间夹着镍合金（Ni-Al）。

公开(公告)号：US20080020495A1

公开(公告)日：2008-01-24

申请号：US11840514

申请日：2007-08-17

申请人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

发明人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

IPC分类号： H01L21/00

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A semiconductor fabricating method including: placing the semiconductor wafer having a film thereon inside of a chamber; generating plasma; detecting a quantity of interference lights for each of at least two wavelengths obtained from a surface of the wafer for a predetermined time period during the etching of the wafer; detecting a first time point at which the detected quantity of interference lights for one of the two wavelengths becomes a maximum and a second time point at which the detected quantity of interference lights for the other wavelength becomes a minimum; determining a state of etching based on a result of comparing a predetermined value with an interval between the first and second time points, wherein both time points are detected by using outputs of a detector for detecting a quantity of the interference lights; and controlling etching in accordance with the determining.

摘要翻译： 一种半导体制造方法，包括：将其上具有膜的半导体晶片放置在室内; 产生等离子体 在晶片的蚀刻期间，在从晶片表面获得的每个至少两个波长的预定时间段内检测干涉光量; 检测所述检测到的两个波长中的一个波长的干扰光的检测量成为最大的第一时间点和所述其他波长的所检测的干涉光量成为最小的第二时间点; 基于将预定值与第一和第二时间点之间的间隔进行比较的结果来确定蚀刻状态，其中通过使用用于检测干涉光量的检测器的输出来检测两个时间点; 以及根据该确定来控制蚀刻。

公开(公告)号：US20070134922A1

公开(公告)日：2007-06-14

申请号：US11354919

申请日：2006-02-16

申请人： Masahito Mori ,  Toshiaki Nishida ,  Naoshi Itabashi ,  Motohiko Yoshigai ,  Hideyuki Kazumi ,  Kazutami Tago

发明人： Masahito Mori ,  Toshiaki Nishida ,  Naoshi Itabashi ,  Motohiko Yoshigai ,  Hideyuki Kazumi ,  Kazutami Tago

IPC分类号： H01L21/302

CPC分类号： H01L21/32136 ,  H01L21/28123 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L22/26 ,  H01L29/66795

摘要： An etching technique capable of applying etching at high selectivity to a transition metal element-containing electrode material layer which is formed on or above a dielectric material layer made of a high-dielectric-constant or “high-k” insulator is provided. To this end, place a workpiece on a lower electrode located within a vacuum processing vessel. The workpiece has a multilayer structure of an electrode material layer which contains therein a transition metal element and a dielectric material layer made of high-k insulator. Then, while introducing a processing gas into the vacuum processing vessel, high-frequency power is applied to inside of the vacuum processing vessel, thereby performing plasma conversion of the introduced processing gas so that the workpiece is etched at its surface. When etching the electrode material layer, an HCl gas is supplied as the processing gas.

摘要翻译： 提供一种能够以高选择性对在由高介电常数或“高k”绝缘体制成的电介质材料层上形成的含过渡金属元素的电极材料层进行蚀刻的蚀刻技术。 为此，将工件放置在位于真空处理容器内的下电极上。 工件具有电极材料层的多层结构，其中包含过渡金属元件和由高k绝缘体制成的电介质材料层。 然后，在将真空​​处理容器内的处理气体导入真空处理容器的内部的同时，向真空处理容器的内部施加高频电力，进行等离子体转换，使工件在其表面被蚀刻。 当蚀刻电极材料层时，作为处理气体供给HCl气体。

公开(公告)号：US07230720B2

公开(公告)日：2007-06-12

申请号：US11256967

申请日：2005-10-25

申请人： Tatehito Usui ,  Takashi Fujii ,  Motohiko Yoshigai ,  Tetsunori Kaji

发明人： Tatehito Usui ,  Takashi Fujii ,  Motohiko Yoshigai ,  Tetsunori Kaji

IPC分类号： G01B9/02 ,  G01B11/02 ,  G01J3/45 ,  G01R31/26

CPC分类号： G01B11/0675 ,  G01B11/0625 ,  H01L21/67069 ,  H01L22/26 ,  Y10T436/106664

摘要： A standard pattern of a differential value of an interference light is set with respect to a predetermined film thickness of a first member to be processed. The standard pattern uses a wavelength as a parameter. Then, an intensity of an interference light of a second member to be processed, composed just like the first member, is measured with respect to each of a plurality of wavelengths so as to obtain a real pattern of an differential value of the measured interference light intensity. The real pattern also uses a wavelength as a parameter. Then, the film thickness of the second member is obtained according to the standard pattern and the real pattern of the differential value.

摘要翻译： 干涉光的微分值的标准图案相对于待处理的第一部件的预定膜厚设定。 标准图案使用波长作为参数。 然后，对于多个波长中的每一个测量与第一构件正好相同的待处理的第二构件的干涉光的强度，以获得所测量的干涉光的差分值的实际图案 强度。 实际图案也使用波长作为参数。 然后，根据标准图案和差分值的实际图案获得​​第二构件的膜厚度。

公开(公告)号：US20060077397A1

公开(公告)日：2006-04-13

申请号：US11289394

申请日：2005-11-30

申请人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

发明人： Tatehito Usui ,  Motohiko Yoshigai ,  Kazuhiro Jyouo ,  Tetsuo Ono

IPC分类号： G01B11/02

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A semiconductor fabricating apparatus for etching a semiconductor wafer, which is placed in a chamber and which has a multiple-layer film composed of a first film formed on a surface thereof and a second film formed on the first film, using plasma generated in the chamber. The semiconductor fabricating apparatus includes a light detector that detects a change in an amount of light with a plurality of wavelengths obtained from the surface of the wafer for a predetermined time during which the second film is etched, and a detection unit that detects a thickness of the first film based on a specific waveform obtained from an output of the detector.

摘要翻译： 一种用于蚀刻半导体晶片的半导体制造装置，该半导体制造装置被放置在腔室中，并且具有由在其表面上形成的第一膜构成的多层膜和在第一膜上形成的第二膜， 。 半导体制造装置包括：光检测器，其在第二膜被蚀刻的预定时间内检测从晶片的表面获得的多个波长的光量的变化;以及检测单元，其检测厚度 基于从检测器的输出获得的特定波形的第一胶片。

公开(公告)号：US06916396B2

公开(公告)日：2005-07-12

申请号：US10224652

申请日：2002-08-21

申请人： Akira Kagoshima ,  Motohiko Yoshigai ,  Hideyuki Yamamoto ,  Daisuke Shiraishi ,  Junichi Tanaka ,  Kenji Tamaki ,  Natsuyo Morioka

发明人： Akira Kagoshima ,  Motohiko Yoshigai ,  Hideyuki Yamamoto ,  Daisuke Shiraishi ,  Junichi Tanaka ,  Kenji Tamaki ,  Natsuyo Morioka

IPC分类号： H01L21/3065 ,  H01L21/00 ,  H01L21/3213 ,  H01L21/66 ,  H05H1/00

CPC分类号： H01L21/67253 ,  G05B2219/45212 ,  H01J37/32935 ,  H01L21/32137 ,  H01L22/20

摘要： An etching system for subjecting a single film to be etched to etching involves a plurality of etching steps in which respective different recipes are applied. The etching system employs recipe generating means which fixes the recipe to be applied to the final etching step, affecting an underlying film making contact with the film to be etched, of the etching steps, to a preset recipe, and which generates a recipe to be applied to the residual etching step on the basis of the results of processing. Etching processing is conducted according to the recipes generated by the recipe generating means.

摘要翻译： 用于对单个膜进行蚀刻的蚀刻系统涉及多个蚀刻步骤，其中应用各自不同的配方。 蚀刻系统使用配方生成装置，其将要应用于最终蚀刻步骤的配方固定到蚀刻步骤的下一个膜，以将蚀刻步骤的蚀刻膜与下一个膜接触到预设配方，并且生成配方 基于处理结果应用于残留蚀刻步骤。 根据食谱产生装置产生的配方进行蚀刻处理。

公开(公告)号：US06903826B2

公开(公告)日：2005-06-07

申请号：US09946504

申请日：2001-09-06

申请人： Tatehito Usui ,  Takashi Fujii ,  Motohiko Yoshigai ,  Tetsunori Kaji ,  Hideyuki Yamamoto

发明人： Tatehito Usui ,  Takashi Fujii ,  Motohiko Yoshigai ,  Tetsunori Kaji ,  Hideyuki Yamamoto

IPC分类号： G01B11/06 ,  G01B9/02

CPC分类号： H01J37/32963 ,  G01B11/0675 ,  H01L22/26

摘要： Standard patterns of differential values of interference light that correspond to a predetermined step height of the first material being processed and standard patterns of differential values of interference light that correspond to a predetermined remaining mask layer thickness of the material are set. These standard patterns use wavelengths as parameters. Then, the intensities of interference light of multiple wavelengths are measured for a second material that has the same structure as the first material. Actual patterns with wavelength as parameter are determined from differential values of the measured interference light intensities. Based on the standard patterns and the actual patterns of the differential values, the step height and the remaining mask layer thickness of the second material are determined.

摘要翻译： 对应于正在处理的第一材料的预定台阶高度的干涉光的差分值的标准图案和对应于材料的预定剩余掩模层厚度的干涉光的差分值的标准图案被设置。 这些标准模式使用波长作为参数。 然后，测量具有与第一材料相同结构的第二材料的多个波长的干涉光的强度。 具有波长作为参数的实际图案由所测量的干涉光强度的差分值确定。 基于标准图案和差分值的实际图案，确定第二材料的台阶高度和剩余掩模层厚度。

公开(公告)号：US20050018207A1

公开(公告)日：2005-01-27

申请号：US10918367

申请日：2004-08-16

申请人： Tatehito Usui ,  Takashi Fujii ,  Motohiko Yoshigai ,  Tetsunori Kaji

发明人： Tatehito Usui ,  Takashi Fujii ,  Motohiko Yoshigai ,  Tetsunori Kaji

IPC分类号： G01B11/06 ,  H01L21/00 ,  H01L21/66 ,  G01B9/02

CPC分类号： G01B11/0675 ,  G01B11/0625 ,  H01L21/67069 ,  H01L22/26 ,  Y10T436/106664

摘要： A standard pattern of a differential value of an interference light is set with respect to a predetermined film thickness of a first member to be processed. The standard pattern uses a wavelength as a parameter. Then, an intensity of an interference light of a second member to be processed, composed just like the first member, is measured with respect to each of a plurality of wavelengths so as to obtain a real pattern of an differential value of the measured interference light intensity. The real pattern also uses a wavelength as a parameter. Then, the film thickness of the second member is obtained according to the standard pattern and the real pattern of the differential value.

摘要翻译： 干涉光的微分值的标准图案相对于待处理的第一部件的预定膜厚设定。 标准图案使用波长作为参数。 然后，对于多个波长中的每一个测量与第一构件正好相同的待处理的第二构件的干涉光的强度，以获得所测量的干涉光的差分值的实际图案 强度。 实际图案也使用波长作为参数。 然后，根据标准图案和差分值的实际图案获得​​第二构件的膜厚度。