公开(公告)号：US08866119B2

公开(公告)日：2014-10-21

申请号：US13051264

申请日：2011-03-18

申请人： Kazuhiko Yamamoto ,  Kenji Aoyama

发明人： Kazuhiko Yamamoto ,  Kenji Aoyama

IPC分类号： H01L29/04 ,  H01L47/00 ,  H01L29/06 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  G11C13/02

CPC分类号： H01L45/04 ,  G11C13/0014 ,  G11C13/025 ,  G11C2213/16 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/149 ,  H01L45/1675

摘要： According to one embodiment, a memory device includes a selection element layer, a nanomaterial aggregate layer, and a fine particle. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer has a plurality of micro conductive bodies aggregated with an interposed gap. The fine particle has at least a surface made of silicon oxynitride. The fine particle is dispersed between the micro conductive bodies in one portion of the nanomaterial aggregate layer piercing the nanomaterial aggregate layer in a thickness direction.

摘要翻译： 根据一个实施例，存储器件包括选择元件层，纳米材料聚集体层和细颗粒。 纳米材料聚集层层叠在选择元件层上。 纳米材料聚集体层具有多个与插入的间隙聚集的微导电体。 细颗粒至少具有由氮氧化硅制成的表面。 微细颗粒分散在纳米材料聚集体层的一部分中的微导电体之间，该纳米材料聚集体层在厚度方向上穿透纳米材料聚集体层。

公开(公告)号：US20120205609A1

公开(公告)日：2012-08-16

申请号：US13235842

申请日：2011-09-19

申请人： Shigeto OSHINO ,  Kenji Aoyama ,  Kazuhiko Yamamoto ,  Shinichi Nakao ,  Kei Watanabe ,  Satoshi Ishikawa

发明人： Shigeto OSHINO ,  Kenji Aoyama ,  Kazuhiko Yamamoto ,  Shinichi Nakao ,  Kei Watanabe ,  Satoshi Ishikawa

IPC分类号： H01L45/00 ,  H01L21/8239 ,  B82Y99/00

CPC分类号： H01L27/101 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/2481 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer.

摘要翻译： 根据一个实施例，存储器件包括下电极层，纳米材料组合层，保护层和上电极层。 纳米材料组装层设置在下电极层上，并且包括通过间隙组装的多个细导体。 保护层设置在纳米材料组装层上，导电，与细导体接触，并包括开口。 上电极层设置在保护层上并与保护层接触。

公开(公告)号：US20120056145A1

公开(公告)日：2012-03-08

申请号：US13018765

申请日：2011-02-01

申请人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L45/00 ,  H01L21/02 ,  B82Y40/00 ,  B82Y30/00

CPC分类号： H01L45/16 ,  B82Y10/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.

摘要翻译： 根据一个实施例，非易失性存储器件包括选择元件层和纳米材料聚集层。 选择元件层包括硅。 纳米材料聚集层层叠在选择元件层上。 纳米材料聚集体层包括分散在微导电体之间的多个间隙中的多个微导电体和微粒。 至少微细颗粒的表面由氧化硅以外的绝缘材料制成。

公开(公告)号：US20120217464A1

公开(公告)日：2012-08-30

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US08895952B2

公开(公告)日：2014-11-25

申请号：US13404678

申请日：2012-02-24

申请人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

发明人： Shigeki Kobayashi ,  Kazuhiko Yamamoto ,  Kenji Aoyama ,  Shigeto Oshino ,  Kei Watanabe ,  Shinichi Nakao ,  Satoshi Ishikawa ,  Takeshi Yamaguchi

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/149

摘要： A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode.

摘要翻译： 通过层叠多个存储单元阵列形成非易失性存储装置，所述存储单元阵列包括多个字线，多个位线和存储单元。 存储单元包括电流整流装置和可变电阻装置，可变电阻装置包括下电极，上电极和包括形成在下电极和上电极之间的导电纳米材料的电阻变化层， 在层叠方向上彼此相邻设置的可变电阻装置在电阻变化层和作为阴极的下部电极之间具有钛氧化物（TiOx），另外在层叠方向上彼此相邻设置的可变电阻装置具有钛 电阻变化层和作为阴极的上部电极之间的氧化物（TiOx）。

公开(公告)号：US08416603B2

公开(公告)日：2013-04-09

申请号：US12973064

申请日：2010-12-20

申请人： Kenji Aoyama ,  Kazuhiko Yamamoto

发明人： Kenji Aoyama ,  Kazuhiko Yamamoto

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： B82Y30/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/149

摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。 第一导电构件沿第一方向延伸。 第二导电构件沿与第一方向相交的第二方向延伸。 连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。 第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。 第一导电构件在第三方向上的电阻值改变。 第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。 第二导电构件在第三方向上的电阻值改变。

公开(公告)号：US20120025159A1

公开(公告)日：2012-02-02

申请号：US12973064

申请日：2010-12-20

申请人： Kenji AOYAMA ,  Kazuhiko Yamamoto

发明人： Kenji AOYAMA ,  Kazuhiko Yamamoto

IPC分类号： H01L45/00 ,  B82Y99/00

CPC分类号： B82Y30/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/149

摘要： According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一导电构件和第二导电构件。 第一导电构件沿第一方向延伸。 第二导电构件沿与第一方向相交的第二方向延伸。 连接到第二导电构件的第一导电构件的一部分朝向第二导电构件突出。 第一导电构件在第一方向上的电阻率低于第一导电构件在第一导电构件的突起的第三方向上的电阻率。 第一导电构件在第三方向上的电阻值改变。 第二导电构件在第二方向上的电阻率低于第二导电构件在第三方向上的电阻率。 第二导电构件在第三方向上的电阻值改变。

公开(公告)号：US08507888B2

公开(公告)日：2013-08-13

申请号：US13018765

申请日：2011-02-01

申请人： Kenji Aoyama ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji Aoyama ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L45/00

CPC分类号： H01L45/16 ,  B82Y10/00 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.

摘要翻译： 根据一个实施例，非易失性存储器件包括选择元件层和纳米材料聚集层。 选择元件层包括硅。 纳米材料聚集层层叠在选择元件层上。 纳米材料聚集体层包括分散在微导电体之间的多个间隙中的多个微导电体和微粒。 至少微细颗粒的表面由氧化硅以外的绝缘材料制成。

公开(公告)号：US20120104352A1

公开(公告)日：2012-05-03

申请号：US13052426

申请日：2011-03-21

申请人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

发明人： Kenji AOYAMA ,  Kazuhiko Yamamoto ,  Satoshi Ishikawa ,  Shigeto Oshino

IPC分类号： H01L45/00 ,  H01L21/62 ,  B82Y10/00 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L45/1675 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149

摘要： According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

摘要翻译： 根据一个实施例，存储器件包括纳米材料组装层，第一电极层和第二电极层。 纳米材料组装层通过微导体之间的间隙由多个微导体的组件形成。 第一电极层设置在纳米材料组装层上。 第二电极层设置在第一电极层上。

公开(公告)号：US09595567B2

公开(公告)日：2017-03-14

申请号：US13585141

申请日：2012-08-14

申请人： Kazuhiko Yamamoto

发明人： Kazuhiko Yamamoto

IPC分类号： H01L29/49 ,  H01L27/24 ,  H01L29/40 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of insulating layers, a plurality of first interconnection layers, a plurality of second interconnection layers, a plurality of memory cells, and a resistance change film. The insulating layers and first interconnection layers are arranged in parallel with the semiconductor substrate. The second interconnection layers are arranged so as to intersect the first interconnection layers. The second interconnection layers are arranged perpendicular to the semiconductor substrate. The memory cells are arranged at intersections of the first and second interconnection layers. Each of the memory cells includes the resistance change film arranged between the first and second interconnection layers. The side of the first interconnection layer in contact with the resistance change film is retreated more in a direction to separate from the second interconnection layer than the side of the insulating layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，多个绝缘层，多个第一互连层，多个第二互连层，多个存储单元和电阻变化膜。 绝缘层和第一互连层与半导体衬底平行布置。 第二互连层被布置成与第一互连层相交。 第二互连层被布置成垂直于半导体衬底。 存储单元布置在第一和第二互连层的交点处。 每个存储单元包括布置在第一和第二互连层之间的电阻变化膜。 与电阻变化膜接触的第一互连层的一侧比与绝缘层的侧面沿着与第二互连层分离的方向更多地退避。