利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

117 条记录 (耗时 0.042 秒)

    OPTIMUM DESIGN METHOD AND APPARATUS, AND PROGRAM FOR THE SAME
    5.
    发明申请
    OPTIMUM DESIGN METHOD AND APPARATUS, AND PROGRAM FOR THE SAME 失效
    最佳设计方法和设备及其相关程序

    公开(公告)号：US20080015828A1

    公开(公告)日：2008-01-17

    申请号：US11778367

    申请日：2007-07-16

    申请人： Teruyoshi Washizawa ,  Akira Asai ,  Masayoshi Tachihara ,  Katsuhiko Sinjo ,  Nobuhiro Yoshikawa

    发明人： Teruyoshi Washizawa ,  Akira Asai ,  Masayoshi Tachihara ,  Katsuhiko Sinjo ,  Nobuhiro Yoshikawa

    IPC分类号： G06F17/10

    CPC分类号： G06F17/11

    摘要： In an optimum design method comprising a first solution determining step of solving an optimization problem of a first evaluation function for a state variable vector with a design variable vector being as a parameter, and a second solution determining step of solving an optimization problem of a second evaluation function for the design variable vector and the state variable vector thus obtained, the second solution determining step includes the steps of computing a gradient vector of the second evaluation function for the design variable vector, computing a first coefficient based on a value of a norm of the gradient vector, computing a search vector based on the first coefficient, computing a second coefficient, and updating the design variable vector based on the second coefficient. The second coefficient computing step includes the first solution determining step, the first solution determining step is executed as an iterative method based on the gradient vector, and the state variable vector is not initialized during iteration. The optimum design method is precisely adaptable for structural changes.

    摘要翻译： 一种最优设计方法，包括：第一解决方案确定步骤，用于以设计变量向量作为参数来求解用于状态变量向量的第一评估函数的优化问题;以及第二解决方案确定步骤，用于求解第二 第二解决方案确定步骤包括以下步骤：计算用于设计变量向量的第二评估函数的梯度向量，基于规范的值计算第一系数;对于设计变量向量和状态变量向量的评估函数， 的梯度向量，基于第一系数计算搜索向量，计算第二系数，并且基于第二系数更新设计变量向量。 第二系数计算步骤包括第一解决方案确定步骤，基于梯度向量作为迭代方法执行第一解决方案确定步骤，并且在迭代期间不初始化状态变量向量。 最佳设计方法适用于结构变化。

    Semiconductor device and method for fabricating the same
    7.
    发明申请
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20050087803A1

    公开(公告)日：2005-04-28

    申请号：US10997127

    申请日：2004-11-24

    申请人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

    发明人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

    IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/01 ,  H01L27/12 ,  H01L29/06 ,  H01L29/76 ,  H01L31/062

    CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  Y10S438/933

    摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

    摘要翻译： 在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。 在基板上形成掩模，然后对基板进行图案化。 以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。 然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。 因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸发部分8。 此后，沟槽7a的壁被氧化。

    Variable capacitance device and process for manufacturing the same
    8.
    发明授权
    Variable capacitance device and process for manufacturing the same 失效
    可变电容器件及其制造方法

    公开(公告)号：US06867107B2

    公开(公告)日：2005-03-15

    申请号：US10456531

    申请日：2003-06-09

    申请人： Akira Asai ,  Teruhito Ohnishi

    发明人： Akira Asai ,  Teruhito Ohnishi

    IPC分类号： H01L21/329 ,  H01L21/84 ,  H01L27/12 ,  H01L29/93 ,  H01L21/20

    CPC分类号： H01L29/66174 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/93

    摘要： A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n− region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n− region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n− region 132 is lower than that in each of the anode 133 and the cathode 131.

    摘要翻译： 一种可变静电电容器件，包括：通过掩埋氧化膜形成在衬底上的半导体层：形成为环形并包含n型掺杂剂的n区132; 邻接于n-区132的外周的阳极133，阳极133形成为环状并含有p型掺杂剂; 以及与n区132的内周相邻的阴极131，所述第三区包含n型掺杂剂，其中所述n区132中的掺杂剂浓度低于阳极133和阴极131中的掺杂浓度 。

    Semiconductor device and method for fabricating the same
    9.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06861316B2

    公开(公告)日：2005-03-01

    申请号：US10637212

    申请日：2003-08-08

    申请人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

    发明人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

    IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/336

    CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  Y10S438/933

    摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

    摘要翻译： 在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。 在基板上形成掩模，然后对基板进行图案化。 以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。 然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。 因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸镀部8。 此后，沟槽7a的壁被氧化。

    Engine variable valve timing system
    10.
    发明授权
    Engine variable valve timing system 失效
    发动机可变气门正时系统

    公开(公告)号：US06860247B2

    公开(公告)日：2005-03-01

    申请号：US10714227

    申请日：2003-11-14

    申请人： Akira Asai ,  Masaki Fukuma ,  Masahiro Naito ,  Kouichi Shimizu ,  Ikuma Takahashi ,  Kazuhiro Tomizawa

    发明人： Akira Asai ,  Masaki Fukuma ,  Masahiro Naito ,  Kouichi Shimizu ,  Ikuma Takahashi ,  Kazuhiro Tomizawa

    IPC分类号： F01L1/344 ,  F01L1/34

    CPC分类号： F01L1/3442 ,  F01L1/022 ,  F01L2001/0537 ,  F01L2001/34426 ,  F01L2001/3443 ,  F01L2001/34433 ,  F01L2001/34469 ,  F01L2001/34483 ,  Y10T74/2102

    摘要： In the variable valve timing system according to the present invention, portions of the intake-side advancing hydraulic line and a retarding hydraulic line respectively constitute annular grooves 104 and 113 for advancing and retarding provided on the intake camshaft 5 bearing surface 5a of the cam cap 4 which supports the camshafts 5 and 6. In addition, portions of the advancing hydraulic line and the retarding hydraulic line for exhaust respectively constitute annular grooves for advancing and retarding 123 and 133 provided on the exhaust camshaft 6 bearing surface 4b of the cam cap 4. Moreover, the annular groove for retarding 113 on the intake camshaft 5 bearing surface 4a and the annular groove for advancing 123 on the exhaust camshaft 6 bearing surface 4b are respectively provided in the center in the width direction of their respective bearing surfaces 4a and 4b.

    摘要翻译： 在根据本发明的可变气门正时系统中，进气侧前进液压管线和延迟液压管路的部分分别构成用于在进气凸轮轴5的凸轮轴5的轴承面5a上设置的用于前进和延迟的环形槽104和113 此外，前进液压管路和排气缓冲液压管路的一部分分别构成用于使设在凸轮盖4的排气凸轮轴6轴承面4b上的123和133的推进和延迟的环形槽 此外，在进气凸轮轴5的承载面4a上延伸的环状槽113和排气凸轮轴6轴承面4b上的行进用环状槽123分别设置在其各自的轴承面4a，4b的宽度方向的中央 。