公开(公告)号：US20050092230A1

公开(公告)日：2005-05-05

申请号：US11009020

申请日：2004-12-13

申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

IPC分类号： C30B1/00 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/322 ,  H01L21/324

CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

公开(公告)号：US06674149B2

公开(公告)日：2004-01-06

申请号：US10009201

申请日：2001-12-10

申请人： Teruhito Ohnishi ,  Akira Asai

发明人： Teruhito Ohnishi ,  Akira Asai

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.

摘要翻译： 在集电极层102上形成用作由i-Si1-xGex层和ap + Si1-xGex层构成的基底的Si1-xGex层111b，在p上形成作为发射极的Si覆盖层111a Si1-xGex层。 发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的n +多晶硅层129b和含有磷的多晶硅层129a组成 在基底开口118中的Si覆盖层111a上形成高浓度。通过抑制Si覆盖层111a以过高的浓度掺杂磷（P）来适当地保持基底层中的杂质浓度分布。 Si覆盖层111a的上部可以含有p型杂质。 因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

公开(公告)号：US06642607B2

公开(公告)日：2003-11-04

申请号：US10061365

申请日：2002-02-04

申请人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

发明人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC分类号： H01L2993

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

摘要翻译： 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

公开(公告)号：US07145168B2

公开(公告)日：2006-12-05

申请号：US10997127

申请日：2004-11-24

申请人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

发明人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  Y10S438/933

摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

摘要翻译： 在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。 在基板上形成掩模，然后对基板进行图案化。 以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。 然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。 因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸发部分8。 此后，沟槽7a的壁被氧化。

公开(公告)号：US20060225642A1

公开(公告)日：2006-10-12

申请号：US10402239

申请日：2003-03-31

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Akira Asai ,  Teruhito Ohnishi

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Akira Asai ,  Teruhito Ohnishi

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B25/04 ,  C30B25/18 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02661 ,  H01L29/1054

摘要： A method of forming semiconductor crystal of the present invention comprises the steps of heating a Si substrate to clean a surface of the Si substrate, epitaxially growing Si crystal on the Si substrate inside a crystal growth chamber at a growth temperature lower than a substrate temperature of the Si substrate in the cleaning step and higher than a growth temperature at which SiGe crystal is epitaxially grown later, and epitaxially growing the SiGe crystal on the Si crystal.

摘要翻译： 本发明的半导体晶体的形成方法包括以下步骤：加热Si衬底以清洁Si衬底的表面，在晶体生长室内的Si衬底上外延生长Si晶体，生长温度低于衬底温度 Si衬底在高于SiGe晶体后来生长的生长温度以及在Si晶体上外延生长SiGe晶体。

公开(公告)号：US07109095B2

公开(公告)日：2006-09-19

申请号：US10396505

申请日：2003-03-26

申请人： Hidenori Notake ,  Teruhito Ohnishi ,  Akira Asai ,  Shigetaka Aoki

发明人： Hidenori Notake ,  Teruhito Ohnishi ,  Akira Asai ,  Shigetaka Aoki

IPC分类号： H01L21/20

CPC分类号： H01L21/0209 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/32134 ,  H01L29/66242

摘要： Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.

公开(公告)号：US06939772B2

公开(公告)日：2005-09-06

申请号：US10882220

申请日：2004-07-02

申请人： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

发明人： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/165 ,  H01L29/36 ,  H01L29/737 ,  H07L21/8249 ,  H07L21/331

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/7378 ,  Y10S438/936

摘要： A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

摘要翻译： 通过在Si衬底上的集电极层102上的外延生长，顺序地生长SiGe间隔层151，包括硼的梯度SiGe基极层152和Si覆盖层153。 在Si覆盖层153上形成有第二沉积氧化物膜112，其具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115，发射极扩散层153a 通过将磷扩散到Si覆盖层153中而形成。当Si覆盖层153生长时，通过使Si覆盖层153仅通过原位掺杂在其上部包含硼而形成， 层154变窄，复合电流降低，从而可以提高电流特性的线性。

公开(公告)号：US06800532B2

公开(公告)日：2004-10-05

申请号：US10620613

申请日：2003-07-17

申请人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

发明人： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC分类号： H01L218222

CPC分类号： H01L29/93 ,  H01L27/0664 ,  H01L27/0808

摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

摘要翻译： 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

公开(公告)号：US20050087803A1

公开(公告)日：2005-04-28

申请号：US10997127

申请日：2004-11-24

申请人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

发明人： Yoshihiro Hara ,  Akira Asai ,  Gaku Sugahara ,  Haruyuki Sorada ,  Teruhito Ohnishi

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/01 ,  H01L27/12 ,  H01L29/06 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823481 ,  Y10S438/933

摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

摘要翻译： 在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。 在基板上形成掩模，然后对基板进行图案化。 以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。 然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。 因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸发部分8。 此后，沟槽7a的壁被氧化。

公开(公告)号：US06867107B2

公开(公告)日：2005-03-15

申请号：US10456531

申请日：2003-06-09

申请人： Akira Asai ,  Teruhito Ohnishi

发明人： Akira Asai ,  Teruhito Ohnishi

IPC分类号： H01L21/329 ,  H01L21/84 ,  H01L27/12 ,  H01L29/93 ,  H01L21/20

CPC分类号： H01L29/66174 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/93

摘要： A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n− region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n− region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n− region 132 is lower than that in each of the anode 133 and the cathode 131.

摘要翻译： 一种可变静电电容器件，包括：通过掩埋氧化膜形成在衬底上的半导体层：形成为环形并包含n型掺杂剂的n区132; 邻接于n-区132的外周的阳极133，阳极133形成为环状并含有p型掺杂剂; 以及与n区132的内周相邻的阴极131，所述第三区包含n型掺杂剂，其中所述n区132中的掺杂剂浓度低于阳极133和阴极131中的掺杂浓度 。