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8 条记录 (耗时 0.019 秒)

    Electrochemical processing apparatus and method
    1.
    发明申请
    Electrochemical processing apparatus and method 审中-公开
    电化学处理装置及方法

    公开(公告)号：US20060070884A1

    公开(公告)日：2006-04-06

    申请号：US11245912

    申请日：2005-10-06

    申请人： Kazutaka Momoi ,  Kazutaka Yanaqita ,  Nobuhiko Sato

    发明人： Kazutaka Momoi ,  Kazutaka Yanaqita ,  Nobuhiko Sato

    IPC分类号： C25D5/02

    CPC分类号： C25D17/10 ,  C25D5/02 ,  C25D11/005 ,  C25D11/02

    摘要： A processing apparatus electrochemically processes part of a first surface of a member having the first surface and a second surface. The processing apparatus includes a support which supports the member to expose the first surface, a first electrode which is arranged to oppose a first portion of the first surface, a second electrode which is arranged to oppose a second portion of the first surface, a third electrode which applies a potential to the member from a second surface side, and a processing bath to fill a space defined by the first and second electrodes and the member with a processing liquid.

    摘要翻译： 一种处理装置，电化学处理具有第一表面和第二表面的构件的第一表面的一部分。 处理装置包括支撑构件以露出第一表面的支撑件，布置成与第一表面的第一部分相对的第一电极，布置成与第一表面的第二部分相对的第二电极，第三电极 电极，其从第二表面侧向构件施加电位;以及处理槽，用处理液填充由第一和第二电极和构件限定的空间。

    INTEGRATED CIRCUIT CHIP MANUFATURING METHOD AND SEMICONDUCTOR DEVICE
    4.
    发明申请
    INTEGRATED CIRCUIT CHIP MANUFATURING METHOD AND SEMICONDUCTOR DEVICE 审中-公开
    集成电路芯片制造方法和半导体器件

    公开(公告)号：US20090085196A1

    公开(公告)日：2009-04-02

    申请号：US12328182

    申请日：2008-12-04

    申请人： Kazutaka Momoi ,  Nobuhiko Sato

    发明人： Kazutaka Momoi ,  Nobuhiko Sato

    IPC分类号： H01L23/12

    CPC分类号： H01L21/76256 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  Y10S438/977

    摘要： This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.

    摘要翻译： 本发明缓和了形成集成电路的半导体区域变薄的芯片形成或封装的难度。 集成电路芯片的制造方法包括：将第一支撑构件接合到具有第一表面和第二表面的半导体衬底的第一表面并且在其第一表面侧上具有包括集成电路的半导体区域的第一接合步骤， 去除接合到第一支撑构件的半导体衬底的第二表面侧部分以离开半导体区域，从而使半导体衬底变薄的薄化步骤，将第二支撑构件接合到第二表面侧的第二接合步骤 薄化的半导体衬底，以及通过切割半导体区域形成芯片的芯片形成步骤。

    Semiconductor substrate, manufacturing method thereof, and semiconductor device
    5.
    发明申请
    Semiconductor substrate, manufacturing method thereof, and semiconductor device 审中-公开
    半导体衬底，其制造方法和半导体器件

    公开(公告)号：US20060124961A1

    公开(公告)日：2006-06-15

    申请号：US10540263

    申请日：2004-12-14

    申请人： Kiyofumi Sakaguchi ,  Kazuya Notsu ,  Kazutaka Momoi ,  Nobuhiko Sato

    发明人： Kiyofumi Sakaguchi ,  Kazuya Notsu ,  Kazutaka Momoi ,  Nobuhiko Sato

    IPC分类号： H01L31/0328

    CPC分类号： H01L29/1054 ,  H01L21/76259 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

    摘要： A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made of the same material as the silicon layer of the strained semiconductor layer. The structure is separated into two parts at the separation layer. When the residue of the separation layer and the SiGe layer are removed, and the surface is planarized by hydrogen annealing, an Si substrate having a strained silicon layer on the uppermost surface is obtained.

    摘要翻译： 在硅衬底上形成分离层。 在分离层上依次形成用作应变感应层的SiGe层和用作应变半导体层的硅层，以制备第一衬底。 第一衬底被结合到由与应变半导体层的硅层相同的材料制成的第二衬底上。 该结构在分离层处分成两部分。 当去除分离层和SiGe层的残余物并且通过氢退火使表面平坦化时，获得在最上表面上具有应变硅层的Si衬底。

    Integrated circuit chip manufacturing method and semiconductor device
    6.
    发明申请
    Integrated circuit chip manufacturing method and semiconductor device 有权
    集成电路芯片制造方法及半导体器件

    公开(公告)号：US20050280119A1

    公开(公告)日：2005-12-22

    申请号：US11149145

    申请日：2005-06-10

    申请人： Kazutaka Momoi ,  Nobuhiko Sato

    发明人： Kazutaka Momoi ,  Nobuhiko Sato

    IPC分类号： H01L21/68 ,  H01L21/762 ,  H01L21/78 ,  H01L23/12

    CPC分类号： H01L21/76256 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  Y10S438/977

    摘要： This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.

    摘要翻译： 本发明缓和了形成集成电路的半导体区域变薄的芯片形成或封装的难度。 集成电路芯片的制造方法包括：将第一支撑构件接合到具有第一表面和第二表面的半导体衬底的第一表面并且在其第一表面侧上具有包括集成电路的半导体区域的第一接合步骤， 去除接合到第一支撑构件的半导体衬底的第二表面侧部分以离开半导体区域，从而使半导体衬底变薄的薄化步骤，将第二支撑构件接合到第二表面侧的第二接合步骤 薄化的半导体衬底，以及通过切割半导体区域形成芯片的芯片形成步骤。

    Integrated circuit chip manufacturing method and semiconductor device
    8.
    发明授权
    Integrated circuit chip manufacturing method and semiconductor device 有权
    集成电路芯片制造方法及半导体器件

    公开(公告)号：US07473617B2

    公开(公告)日：2009-01-06

    申请号：US11149145

    申请日：2005-06-10

    申请人： Kazutaka Momoi ,  Nobuhiko Sato

    发明人： Kazutaka Momoi ,  Nobuhiko Sato

    IPC分类号： H01L21/30

    CPC分类号： H01L21/76256 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  Y10S438/977

    摘要： This invention moderates the difficulty in chip formation or packaging which accompanies thinning of a semiconductor region where an integrated circuit is formed. An integrated circuit chip manufacturing method includes a first bonding step of bonding a first support member to a first surface of a semiconductor substrate which has the first surface and a second surface and has a semiconductor region including an integrated circuit on a first surface side thereof, a thinning step of removing a second surface-side portion of the semiconductor substrate bonded to the first support member to leave the semiconductor region, thereby thinning the semiconductor substrate, a second bonding step of bonding a second support member to the second surface side of the thinned semiconductor substrate, and a chip forming step of forming chips by cutting the semiconductor region.

    摘要翻译： 本发明缓和了形成集成电路的半导体区域变薄的芯片形成或封装的难度。 集成电路芯片的制造方法包括：将第一支撑构件接合到具有第一表面和第二表面的半导体衬底的第一表面并且在其第一表面侧上具有包括集成电路的半导体区域的第一接合步骤， 去除接合到第一支撑构件的半导体衬底的第二表面侧部分以离开半导体区域，从而使半导体衬底变薄的薄化步骤，将第二支撑构件接合到第二表面侧的第二接合步骤 薄化的半导体衬底，以及通过切割半导体区域形成芯片的芯片形成步骤。