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公开(公告)号：US5459342A
公开(公告)日：1995-10-17
申请号：US146312
申请日：1993-11-02
IPC分类号： H01L21/82 , G06F11/20 , H01L27/118 , H03K19/173 , H01L21/70 , H01L27/00 , H03K19/177
CPC分类号： H03K19/17764
摘要： A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.
摘要翻译： 现场可编程门阵列包括：多个具有逻辑电路的电路块; 至少一个具有逻辑电路的备用电路块; 一组互连，其包括至少一个互连，用于可编程地连接至少一个所述电路块和所述至少一个备用电路; 以及至少一个连接元件，其设置在所述一组互连件的互连上，其在编程时将其状态从打开状态转变为关闭状态，反之亦然。 当任何一个电路块有缺陷时，由于可以用备用电路块代替有缺陷的电路块，可以通过编程连接装置来保持逻辑电路的所需功能，从而提高了现场的产量 可编程门阵列，从而降低其制造成本。
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2.发明授权Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires 失效具有传输门的现场可编程门阵列和用于编程线的连接的半导体集成电路
公开(公告)号：US5539331A
公开(公告)日：1996-07-23
申请号：US237631
申请日：1994-05-04
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/177 , H03K19/17704
摘要： A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.
摘要翻译： 现场可编程门阵列包括：由多条第一线组成的第一线组（8）; 由多条第二线组成的第二线组（7） 切换部分（9）提供了第一和第二线组（8,7）的第一和第二线之间的至少一个交点，用于在编程时确定两者之间的连接和断开; 以及响应于高栅极电压而导通的第一传输门（4）和响应于低栅极电压导通的第二传输门（5）的基站（6B），第一和第二传输门的栅极 （4,5）作为公共栅极彼此连接，或者当编程的输入和输出端子和第一和第二传输门（4,5）的公共栅极时，由开关部分作为公共栅极彼此连接 ）分别连接到第一线组（8）的任何第一线。 提供不同长度的接线用于连接现场可编程门阵列内的电路元件，第一长度的导线比第二较长长度的导线多。 不同长度的电线数量根据电线长度的-2.5功率而变化。
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公开(公告)号：US5764588A
公开(公告)日：1998-06-09
申请号：US848223
申请日：1997-04-29
申请人： Kazutaka Nogami , Fumitoshi Hatori
发明人： Kazutaka Nogami , Fumitoshi Hatori
摘要： A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.
摘要翻译： 实现具有比常规存储器件更高密度的单端口存储器或多端口存储器，同时使用相同的设计规则，通过减少每列或端口的位线数量以减少布线空间和尺寸 整个记忆 存储电路包括以矩阵形式布置多个存储单元的存储单元阵列，每个存储单元具有至少一个读端口; 每个连接到存储单元阵列的存储单元中的一行排列的存储单元的字线以及与存储单元阵列的存储单元中的n行（n> / = 2）对齐的存储单元连接的位线。 共享n位线的存储单元的存取晶体管的电流驱动能力设定为满足1：2：的关系。 。 。 ：2n-1。 这导致位线的数量和存储器的面积减少。
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公开(公告)号：US5498978A
公开(公告)日：1996-03-12
申请号：US237851
申请日：1994-05-04
IPC分类号： H01L21/82 , G11C17/16 , H01L27/118 , H03K19/173 , H03K19/177 , H01H37/76 , H03K17/687
CPC分类号： H03K19/17796 , G11C17/16 , H03K19/17704
摘要： A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . . ) between which the programmable element to be programmed is connected and an intermediate voltage between the first and second wirings between which the programmable element not to be programmed is connected, the intermediate voltage being lower than the programming voltage to such an extent as not to affect state of the programmable elements (A11, A12, A13, . . . ).
摘要翻译： 现场可编程门阵列包括：由多个第一布线（C1，C2，C3 ...）组成的第一布线组; 由多个第二布线（R1，R2，R3 ...）组成的第二布线组; 在第一布线和第二布线之间的多个交点中的至少一个布置成阵列图案的多个可编程元件（A11，A12，A13 ...），每个可编程元件连接到每个第一布线 （C1，C2，C3，...）和其另一端的每个第二布线（R1，R2，R3 ...），并通过施加在第一布线 以及用于将所述第一和第二布线之间的连接切换到所述两条布线之间的断开的第二布线，反之亦然; 以及用于在第一和第二布线（C1，C2，C3，...，R1，R2，R3等）之间施加编程电压的电压供应部分（CD1，RD1），其中要编程的可编程元件 所述第一和第二布线之间的中间电压被连接在可编程元件不被编程之间的中间电压，所述中间电压低于编程电压至不影响可编程元件（A11，A12， A13，...）。
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公开(公告)号：US4757217A
公开(公告)日：1988-07-12
申请号：US11882
申请日：1987-02-06
IPC分类号： G11C11/403 , G11C11/406 , H03K3/356
CPC分类号： G11C11/406
摘要： This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.
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公开(公告)号：US4984208A
公开(公告)日：1991-01-08
申请号：US364529
申请日：1989-06-12
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.
摘要翻译： 动态读/写存储器，其中在读/写周期内执行刷新以使写恢复时间不延长。 对应于当前地址的字线在写入周期内连续地进行操作。 当写入操作完成时，字线被操作，从而启动刷新。 字线只能在读取周期的给定时间段内运行。
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公开(公告)号：US4853897A
公开(公告)日：1989-08-01
申请号：US128946
申请日：1987-12-04
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4099
CPC分类号： G11C11/4094 , G11C11/4085 , G11C11/4099
摘要： The invention discloses a semiconductor memory device possessing high operational reliability. In the semiconductor memory device according to the invention, a plurality of well regions of a conductivity type different from that of a semiconductor substrate are formed in the semiconductor substrate, and a memory cell array and a bit line driver are formed in other well regions, situated away from each other. With this arrangement, the number of signal lines to be connected to the well region in which the memory cell array is formed can be reduced, and the adverse influence of minority carriers generated upon operation of the bit line driver can be prevented. With this arrangement, well bias can be applied only to memory cell array. As a result, the operational reliability of the semiconductor memory device can be improved.
摘要翻译： 本发明公开了具有高操作可靠性的半导体存储器件。 在根据本发明的半导体存储器件中，在半导体衬底中形成不同于半导体衬底的导电类型的多个阱区，并且在其它阱区中形成存储单元阵列和位线驱动器， 远离彼此。 通过这种布置，可以减少要连接到其上形成存储单元阵列的阱区的信号线的数量，并且可以防止在位线驱动器的操作时产生的少数载流子的不利影响。 利用这种布置，阱偏压仅可应用于存储单元阵列。 结果，可以提高半导体存储器件的操作可靠性。
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8.发明授权Virtual type static semiconductor memory device including refresh detector circuitry 失效包括刷新检测器电路的虚拟型静态半导体存储器件
公开(公告)号：US4939695A
公开(公告)日：1990-07-03
申请号：US268927
申请日：1988-11-09
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.
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公开(公告)号：US4905192A
公开(公告)日：1990-02-27
申请号：US175252
申请日：1988-03-30
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.
摘要翻译： 半导体存储器件包括存储单元阵列，备用存储单元阵列，用于指定存储单元阵列的地址的第一寻址电路，用于指定备用存储单元阵列的地址的第二寻址电路，用于激活的驱动电路 由第一和第二寻址电路中的每一个指定的选择线，用于基于存储单元阵列是否具有缺陷或故障来产生预定输出的程序电路，以及响应于来自程序电路的输出的选择电路， 当存储器阵列单元中没有故障时，在更早的定时向指定的选择线提供激活信号，并且当存在故障时提供延迟了选择备用存储单元阵列所需的时间的激活信号 存储单元阵列。
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公开(公告)号：US4769792A
公开(公告)日：1988-09-06
申请号：US923958
申请日：1986-10-28
申请人： Kazutaka Nogami , Takayasu Sakurai , Syuso Fujii
发明人： Kazutaka Nogami , Takayasu Sakurai , Syuso Fujii
CPC分类号： G11C7/12 , G11C11/406 , G11C5/145 , G11C8/08
摘要： Two or more voltage bootstrap circuits are included, and are sequentially operated. A continuous data write/read operation can be performed at a high speed. One of the two voltage bootstrap circuits is used for the data write/read operation and the other thereof is used for the refresh operation, thereby shortening the time required for refreshing.
摘要翻译： 包括两个或多个电压自举电路，并且被依次操作。 可以高速执行连续的数据写入/读取操作。 两个电压自举电路中的一个用于数据写入/读取操作，另一个用于刷新操作，从而缩短刷新所需的时间。
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