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    Motion vector detecting device capable of accommodating a plurality of predictive modes
    1.
    发明授权
    Motion vector detecting device capable of accommodating a plurality of predictive modes 失效
    能够适应多种预测模式的运动矢量检测装置

    公开(公告)号：US06674798B2

    公开(公告)日：2004-01-06

    申请号：US09961139

    申请日：2001-09-24

    申请人： Kazuya Ishihara ,  Shinichi Uramoto ,  Shinichi Nakagawa ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Atsuo Hanami

    发明人： Kazuya Ishihara ,  Shinichi Uramoto ,  Shinichi Nakagawa ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Atsuo Hanami

    IPC分类号： H04N736

    CPC分类号： H04N5/145 ,  G06T7/223 ,  G06T7/231 ,  G06T2207/10016 ,  H04N19/433 ,  H04N19/51

    摘要： A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode. It is possible to simultaneously detect motion vectors according to a plurality of predictive modes. It is possible to detect motion vectors employed for moving image predictive compensation in accordance with a plurality of predictive modes at a high speed with a small hardware volume.

    摘要翻译： 处理器阵列包括对应于作为当前图像像素块的模板块的各个像素的矩阵排列的元件处理器。 每个元素处理器存储作为对应的参考图像像素块的搜索窗口块的像素数据，并获得关于模板块像素数据的评估函数值分量。 求和部分根据多种预测模式对从处理器阵列的相应元件处理器接收的评估函数分量进行排序，并对各种类型的组件求和，以形成各个预测模式的评估函数值。 比较部分比较从每个预测模式的求和部分接收的评估函数值，以确定提供最佳相似度的位移矢量作为每个预测模式的运动矢量。 可以根据多种预测模式同时检测运动矢量。 根据具有小硬件体积的高速的多种预测模式，可以检测用于运动图像预测补偿的运动矢量。

    Unit for detecting motion vector for motion compensation
    2.
    发明授权
    Unit for detecting motion vector for motion compensation 失效
    用于检测运动补偿运动矢量的单元

    公开(公告)号：US5949486A

    公开(公告)日：1999-09-07

    申请号：US795217

    申请日：1997-02-05

    申请人： Kazuya Ishihara ,  Shinichi Uramoto ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Atsuo Hanami ,  Shinichi Masuda

    发明人： Kazuya Ishihara ,  Shinichi Uramoto ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Atsuo Hanami ,  Shinichi Masuda

    IPC分类号： H04N19/50 ,  H03M7/30 ,  H03M7/36 ,  H04N5/14 ,  H04N19/423 ,  H04N19/436 ,  H04N19/51 ,  H04N7/12

    CPC分类号： H04N19/433 ,  H04N19/51 ,  H04N5/145

    摘要： Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

    摘要翻译： 与模板块和搜索窗口块的像素相对应地布置的每个元素处理器分别包括彼此并行提供的用于存储搜索窗口块像素数据的A寄存器和B寄存器，以及用于存储模板块的T寄存器 像素数据。 通过A和B寄存器中的第一个和存储在T寄存器中的像素数据执行运动矢量评估值计算，而操作数据从A和B中的第一个传送到A和B寄存器中的第二个， B与计算操作并行登记，用于存储下一个搜索窗口的头部搜索窗口块像素数据。 以良好的编码效率高速检测运动矢量。

    Program execution control device having addressability in accordance with M series pseudo-random number sequence
    4.
    发明授权
    Program execution control device having addressability in accordance with M series pseudo-random number sequence 失效
    具有符合M系列伪随机数序列的寻址能力的程序执行控制装置

    公开(公告)号：US5651123A

    公开(公告)日：1997-07-22

    申请号：US460947

    申请日：1995-06-05

    申请人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    发明人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/321 ,  G06F2207/7219

    摘要： Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

    摘要翻译： 程序的指令按照程序地址的顺序存储在指令存储器中根据M系列伪随机数序列顺序指定的地址处。 伪随机数程序计数器具有用于产生相同M系列伪随机数序列的反馈移位寄存器，并且基于生成的伪随机数将从指令存储器读出的指令的地址应用于指令存储器， 以及来自指令解码器的跳转地址和选择信号。 结果，从指令存储器中读取指令并按程序地址的顺序执行。 反馈移位寄存器可以实现为小规模电路并且可以高速运行。

    Motion vector detecting apparatus
    6.
    发明授权
    Motion vector detecting apparatus 失效
    运动矢量检测装置

    公开(公告)号：US06765965B1

    公开(公告)日：2004-07-20

    申请号：US09425214

    申请日：1999-10-22

    申请人： Atsuo Hanami ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Kazuya Ishihara

    发明人： Atsuo Hanami ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Kazuya Ishihara

    IPC分类号： H04B166

    CPC分类号： H04N19/159 ,  H04N5/145 ,  H04N19/523 ,  H04N19/57 ,  H04N19/577

    摘要： A plurality of motion detecting units of which at least a template block size, i.e., the number of estimation pixels, or a search area size is different among the motion detecting units are used adaptively according to the characteristic of, or the prediction coding type of, a target picture. This enables efficient motion vector detection to be accomplished without increasing the amount of hardware or power consumption.

    摘要翻译： 根据运动检测单元的特性或预测编码类型，运动检测单元中的至少模板块大小（即，估计像素的数量）或搜索区域大小不同的多个运动检测单元 ，目标图片。 这使得能够在不增加硬件或功耗的情况下实现有效的运动矢量检测。

    Control signal generating device generating various control signals using storage unit having small storage capacity
    9.
    发明授权
    Control signal generating device generating various control signals using storage unit having small storage capacity 失效
    控制信号发生装置利用具有小存储容量的存储单元产生各种控制信号

    公开(公告)号：US5740088A

    公开(公告)日：1998-04-14

    申请号：US530497

    申请日：1995-09-19

    申请人： Shinichi Nakagawa ,  Kiyofumi Kawamoto ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami

    发明人： Shinichi Nakagawa ,  Kiyofumi Kawamoto ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami

    IPC分类号： H03K3/84 ,  G05B19/07 ,  G06F7/00 ,  G06F7/58 ,  H04L7/00 ,  G06F1/02

    CPC分类号： G05B19/07 ,  G06F7/00

    摘要： A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

    摘要翻译： 第一伪随机数产生电路响应于时钟信号顺序地向匹配检测电路提供输出信号。 第二伪随机数发生电路产生初始值，然后响应于来自匹配检测电路的输出信号和时钟信号，向存储装置依次提供输出信号。 以输出信号作为地址的数据作为来自存储装置的输出信号提供。 当匹配检测电路检测输出信号之间的匹配时，匹配检测电路将输出信号提供给第二伪随机数产生电路和与逻辑电路。 如上所述，当提供匹配检测电路的输出信号时，来自存储装置的输出信号被提供为相应的输出控制信号。

    Variable-length code table and variable-length coding device
    10.
    发明授权
    Variable-length code table and variable-length coding device 失效
    可变长度码表和可变长度编码装置

    公开(公告)号：US5539401A

    公开(公告)日：1996-07-23

    申请号：US483035

    申请日：1995-06-07

    申请人： Satoshi Kumaki ,  Kazuya Ishihara ,  Shinichi Nakagawa ,  Atsuo Hanami

    发明人： Satoshi Kumaki ,  Kazuya Ishihara ,  Shinichi Nakagawa ,  Atsuo Hanami

    IPC分类号： H04N19/60 ,  G06T9/00 ,  H03M7/42 ,  H04N1/41 ,  H04N1/411 ,  H04N19/423 ,  H04N19/426 ,  H04N19/625 ,  H04N19/93 ,  H03M7/40

    CPC分类号： H03M7/42 ,  G06T9/005 ,  H04N1/411

    摘要： A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value. Each address includes a first region having a value and a length uniquely specified based on the class including the second equal-length component, a second region storing the first equal-length component, and a third region storing the second equal-length component, and is constructed to have a fixed length as a whole. Region lengths of the second and third regions are determined correspondingly to the class including the second equal-length component, and each are specifically determined to have the minimum value required for storing the maximum values of the absolute values of the first and second equal-length components of the combinations of the equal-length components included in the corresponding class.

    摘要翻译： 用于从由一组第一和第二等长分量形成的数据产生可变长度码的可变长度码表存储在由一组等长分量唯一分配的地址a相应的地址 可变长度代码和可变长度代码的代码长度。 预先选择第一和第二等长分量的组合，使得第一等长分量的绝对值的最大值随着与其组合的第二等长分量的绝对值减小而增加。 第二等长分量根据绝对值的大小被分类为多个类别。 每个地址包括具有基于包括第二等长分量的类别唯一地指定的值和长度的第一区域，存储第一等长分量的第二区域和存储第二等长分量的第三区域，以及 被构造为具有整体的固定长度。 对应于包括第二等长分量的类别确定第二和第三区域的区域长度，并且每个具体确定为具有存储第一和第二等长度的绝对值的最大值所需的最小值 相应类别中包括的等长分量组合的组成部分。