利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

57 条记录 (耗时 0.027 秒)

    Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices
    4.
    发明授权
    Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices 失效
    运动矢量检测装置提高运动矢量的检测速度和采用相同装置的系统

    公开(公告)号：US06968011B2

    公开(公告)日：2005-11-22

    申请号：US10155993

    申请日：2002-05-29

    申请人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Atsuo Hanami ,  Yoshinori Matsuura

    发明人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Atsuo Hanami ,  Yoshinori Matsuura

    IPC分类号： H04N19/50 ,  H04N5/14 ,  H04N19/503 ,  H04N19/543 ,  H04N19/57 ,  H04N7/12

    CPC分类号： H04N5/145 ,  H04N19/436 ,  H04N19/51

    摘要： The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.

    摘要翻译： 控制电路控制保持在输入部分中的模板块数据的输出，使得操作部分内的多个操作单元被提供有彼此不同的不相邻模板块的数据。 操作部分内的操作单元根据提供给它的模板块数据来检测运动矢量。 因此，除了不需要运动矢量检测的显示画面上的区域中的模板块中的运动矢量检测分布在多个运算单元中。 因此，在相同的动作时间内，与现有的情况相比，可以在比垂直方向或水平方向更宽的范围内进行运动矢量搜索。

    Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow
    5.
    发明授权
    Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow 失效
    用于检测缓冲器溢出中的图像的顶部位置的图像压缩编码装置和方法

    公开(公告)号：US06907068B2

    公开(公告)日：2005-06-14

    申请号：US09922695

    申请日：2001-08-07

    申请人： Hiroshi Segawa ,  Satoshi Kumaki ,  Yoshinori Matsuura

    发明人： Hiroshi Segawa ,  Satoshi Kumaki ,  Yoshinori Matsuura

    IPC分类号： H04N19/50 ,  H03M7/30 ,  H04N19/102 ,  H04N19/146 ,  H04N19/423 ,  H04N19/70 ,  H04N7/12

    CPC分类号： H04N19/152 ,  H04N19/132 ,  H04N19/159 ,  H04N19/172 ,  H04N19/46 ,  H04N19/61

    摘要： To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (7A) executes a picture top detection processing for discarding image compression data (S2) until a top of a picture of the image compression data (S2) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor (5) brings a detection start register (8) into a set state and causes the picture top detector (7A) to execute the picture top detection processing during an overflow of an output buffer (3a), and executes an interruption processing of rewriting, as a value of a write address register (9), an address where a top of an overflow picture to be a picture causing the overflow is stored.

    摘要翻译： 提供一种能够最小化在输出缓冲器溢出期间在再现图像上引起的图像质量劣化的图像压缩编码装置和方法。 图像顶部检测器（7A）执行用于丢弃图像压缩数据（S2）的图像顶部检测处理，直到在检测到开始地址期间检测到图像压缩数据（S 2）的图像的顶部，并重新开始 检测到图像顶部后的正常操作。 处理器（5）使检测开始寄存器（8）进入设置状态，并使图像顶部检测器（7A）在输出缓冲器（3a）溢出期间执行图像顶部检测处理，并执行中断 作为写入地址寄存器（9）的值的重写处理，存储溢出图像的顶部作为导致溢出的图像的地址。

    Motion estimation method and apparatus for interrupting computation which is determined not to provide solution
    6.
    发明授权
    Motion estimation method and apparatus for interrupting computation which is determined not to provide solution 有权
    用于中断计算的运动估计方法和装置，其被确定为不提供解决方案

    公开(公告)号：US06687299B2

    公开(公告)日：2004-02-03

    申请号：US09261171

    申请日：1999-03-03

    申请人： Toyohiko Yoshida ,  Kazuya Ishihara ,  Yoshinori Matsuura ,  Tetsuya Matsumura ,  Vasily Moshnyaga

    发明人： Toyohiko Yoshida ,  Kazuya Ishihara ,  Yoshinori Matsuura ,  Tetsuya Matsumura ,  Vasily Moshnyaga

    IPC分类号： H04B166

    CPC分类号： H04N5/145 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/51 ,  H04N19/557

    摘要： A motion estimation method capable of setting an optimum threshold value and allowing high speed processing includes the steps of: sequentially selecting one of blocks to be searched from a search range; sequentially calculating a difference between corresponding sample values of a reference block and one of blocks to be searched and accumulating an absolute value of difference; comparing an intermediate result of an accumulation value and a prescribed threshold value for a prescribed number of samples and interrupting the step of accumulating the absolute value of difference when the intermediate result exceeds the prescribed threshold value; and making one of blocks to be searched having a minimum final result of the accumulation value correspond to the reference block. The prescribed threshold value is dependent on the reference block. It is noted that the motion estimation apparatus is also disclosed.

    摘要翻译： 能够设定最佳阈值并允许高速处理的运动估计方法包括以下步骤：从搜索范围顺序选择要搜索的块之一; 顺序地计算参考块的对应样本值与要搜索的块中的一个的差值，并累加差值的绝对值; 比较规定数量样本的累积值和规定阈值的中间结果，并且当中间结果超过规定阈值时中断累积差分绝对值的步骤; 并且使具有累积值的最小最终结果的要搜索的块之一对应于参考块。 规定的阈值取决于参考块。 注意，还公开了运动估计装置。

    Semiconductor storage device with macro-cell with monitoring of input data
    7.
    发明授权
    Semiconductor storage device with macro-cell with monitoring of input data 失效
    具有监控输入数据的宏单元的半导体存储设备

    公开(公告)号：US5701267A

    公开(公告)日：1997-12-23

    申请号：US578892

    申请日：1995-12-27

    申请人： Shinichi Masuda ,  Satoshi Kumaki ,  Yoshinori Matsuura

    发明人： Shinichi Masuda ,  Satoshi Kumaki ,  Yoshinori Matsuura

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C7/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/22 ,  G11C29/56 ,  G11C13/00

    CPC分类号： G11C7/00 ,  G11C29/003

    摘要： It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

    摘要翻译： 本发明的目的是实现诸如FIFO存储器等的宏小区中的输入数据的旁路，以便于关于其他宏小区的测试和评估。 旁路路径（6）设置在FIFO存储器（1）中的输入端口（DI）和输出端口（DO）之间，并且数据旁路选择器（8）还被设置用于选择旁路路径（6）和 读位线（RBL）的读出放大器（7）。 然后，在测试模式中，将第一选择器控制信号（S）设置为L电平，将相反相位的第二选择器控制信号（+ E，ovs S + EE）设置为H电平。 因此，在测试模式中，从输入端口（DI）输入的数据通过旁路路径（6）从输出端口（DO）输出，而不经由存储单元（MC1-MCX）输出。

    RS flip-flop
    8.
    发明授权
    RS flip-flop 失效
    RS触发器

    公开(公告)号：US5208487A

    公开(公告)日：1993-05-04

    申请号：US862661

    申请日：1992-04-01

    申请人： Yoshinori Matsuura ,  Shinichi Nakagawa ,  Tetsuya Matsumura

    发明人： Yoshinori Matsuura ,  Shinichi Nakagawa ,  Tetsuya Matsumura

    IPC分类号： H03K3/037 ,  H03K3/356

    CPC分类号： H03K3/037 ,  H03K3/356017 ,  H03K3/356069

    摘要： A logic circuit outputs a logic signal in response to set inputs and a reset input. This logic signal is applied to output terminals through a latch circuit. When outputs Q and Q of the RS flip-flop maintain a previous state, the latch circuit is activated by a control signal applied from an OR gate to hold a previous logic signal received from the logic circuit. Thus, the logic circuit and latch circuit are arranged on a signal path from input terminals to output terminals. These logic circuit and latch circuit do not include a series connection of transistors and, therefore, is operable at high speed in response to the inputs. Consequently, the outputs Q and Q have excellent response characteristics relative to the set and reset inputs, to enable a high-speed operation.

    摘要翻译： 逻辑电路根据设定输入和复位输入输出逻辑信号。 该逻辑信号通过锁存电路施加到输出端子。 当RS触发器的输出Q和＆amp; upbar＆Q保持先前状态时，锁存电路由从或门施加的控制信号激活，以保持从逻辑电路接收到的先前的逻辑信号。 因此，逻辑电路和锁存电路被布置在从输入端子到输出端子的信号路径上。 这些逻辑电路和锁存电路不包括晶体管的串联连接，因此可以响应于输入以高速操作。 因此，输出Q和＆amp; upbar＆Q相对于设定和复位输入具有优异的响应特性，以实现高速运行。

    Data transfer system
    9.
    发明授权
    Data transfer system 失效
    数据传输系统

    公开(公告)号：US5303353A

    公开(公告)日：1994-04-12

    申请号：US862660

    申请日：1992-04-01

    申请人： Yoshinori Matsuura ,  Shinichi Uramoto ,  Tetsuya Matsumura

    发明人： Yoshinori Matsuura ,  Shinichi Uramoto ,  Tetsuya Matsumura

    IPC分类号： G06F13/28 ,  G06F13/38 ,  G06F13/40

    CPC分类号： G06F13/4018

    摘要： A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connected to the data bus. Even if there is generated data of two words to be transferred in these registers, the data operation part, the RAM and the ROM, the data bus can simultaneously transfer the data. In order to prevent conflict of data on the data bus, there are provided a bus driver, a multiplexer and a bus selector.

    摘要翻译： 数据总线具有2个字的位长度，并被分成两个位组，每个位对应一个字。 因此，数据总线可以同时传输两个字的数据。 寄存器，CPU的数据操作部分，RAM和ROM连接到数据总线。 即使存在要在这些寄存器中传送的两个字的数据，数据操作部分，RAM和ROM，数据总线也可以同时传送数据。 为了防止数据总线上的数据冲突，提供了总线驱动器，多路复用器和总线选择器。

    Picture coding device where the quantization step is adjusted in response to a motion vector
    10.
    发明授权
    Picture coding device where the quantization step is adjusted in response to a motion vector 失效
    图像编码装置，其中根据运动矢量调整量化步长

    公开(公告)号：US6011589A

    公开(公告)日：2000-01-04

    申请号：US805326

    申请日：1997-02-24

    申请人： Yoshinori Matsuura ,  Hiroshi Segawa ,  Shinichi Masuda

    发明人： Yoshinori Matsuura ,  Hiroshi Segawa ,  Shinichi Masuda

    IPC分类号： H04N11/04 ,  H03M7/36 ,  H04N19/107 ,  H04N19/11 ,  H04N19/126 ,  H04N19/134 ,  H04N19/139 ,  H04N19/154 ,  H04N19/176 ,  H04N19/189 ,  H04N19/196 ,  H04N19/423 ,  H04N19/50 ,  H04N19/503 ,  H04N19/51 ,  H04N19/61 ,  H04N19/625 ,  H04N19/85 ,  H04N7/18

    CPC分类号： H04N19/152 ,  H04N19/107 ,  H04N19/126 ,  H04N19/176 ,  H04N19/61 ,  H04N19/137 ,  H04N19/149 ,  H04N19/15

    摘要： An object of the present invention is to improve visual picture quality. A picture signal is divided into a plurality of macro blocks and coding is conducted in macro block units. The coding is conducted including quantization process by a quantization portion. A motion compensation portion outputs the quantity of motion, L, in macro block units. An average quantity of motion, L.sub.ave, of a reference picture stored in a frame memory is outputted from a division portion. A control portion compares the quantity of motion L with two reference values relative to the average quantity of motion L.sub.ave and makes a correction to lower the quantization step in the quantization portion for macro blocks whose quantity of motion L is between the reference values. Accordingly, picture quality is improved in part of picture where motion is small and deterioration of visual picture quality is noticeable. At the same time, since the correction is not applied to picture with such slow motion that deterioration of picture quality is small, redundancy of coded signal does not unnecessarily increase.

    摘要翻译： 本发明的目的是提高视觉画质。 图像信号被分成多个宏块，以宏块为单位进行编码。 进行包括量化部的量化处理的编码。 运动补偿部以宏块为单位输出运动量L。 从分割部分输出存储在帧存储器中的参考图像的平均运动量Lave。 控制部分将运动量L与相对于平均移动量Lave的两个参考值进行比较，并且对运动量L在参考值之间的宏块进行量化部分中的量化步长的校正。 因此，在运动少的图像的一部分中，图像质量得到改善，视觉画面质量的恶化是显着的。 同时，由于校正不适用于图像质量差劣化的慢速图像，编码信号的冗余度不会不必要地增加。