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    Program execution control device having addressability in accordance with M series pseudo-random number sequence
    5.
    发明授权
    Program execution control device having addressability in accordance with M series pseudo-random number sequence 失效
    具有符合M系列伪随机数序列的寻址能力的程序执行控制装置

    公开(公告)号：US5651123A

    公开(公告)日：1997-07-22

    申请号：US460947

    申请日：1995-06-05

    申请人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    发明人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/321 ,  G06F2207/7219

    摘要： Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

    摘要翻译： 程序的指令按照程序地址的顺序存储在指令存储器中根据M系列伪随机数序列顺序指定的地址处。 伪随机数程序计数器具有用于产生相同M系列伪随机数序列的反馈移位寄存器，并且基于生成的伪随机数将从指令存储器读出的指令的地址应用于指令存储器， 以及来自指令解码器的跳转地址和选择信号。 结果，从指令存储器中读取指令并按程序地址的顺序执行。 反馈移位寄存器可以实现为小规模电路并且可以高速运行。

    Data processor and data processing method reduced in power consumption during memory access
    6.
    发明授权
    Data processor and data processing method reduced in power consumption during memory access 失效
    数据处理器和数据处理方法降低了存储器访问期间的功耗

    公开(公告)号：US06918002B2

    公开(公告)日：2005-07-12

    申请号：US10053545

    申请日：2002-01-24

    申请人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Hiroshi Segawa ,  Atsuo Hanami ,  Vasile Mosneaga

    发明人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Hiroshi Segawa ,  Atsuo Hanami ,  Vasile Mosneaga

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F12/00 ,  G06F12/04 ,  G06F13/42

    CPC分类号： G06F13/4239 ,  G11C7/1006 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/151

    摘要： When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

    摘要翻译： 当CPU将数据写入存储器时，0检测电路从数据中检测出具有值0的位数。 当具有0的比特数等于或大于具有1的比特数时，在选择器的控制下，从CPU输出的数据被提供给存储器。 当具有0的比特数少于具有1的比特数时，从CPU输出的数据被反转，并在选择器的控制下提供给存储器。 因此，可以平均地减少存储器中的每个存储单元从0到1或从1到0的重写频率。 因此，可以减少数据写入模式中的存储器的功耗。

    Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow
    7.
    发明授权
    Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow 失效
    用于检测缓冲器溢出中的图像的顶部位置的图像压缩编码装置和方法

    公开(公告)号：US06907068B2

    公开(公告)日：2005-06-14

    申请号：US09922695

    申请日：2001-08-07

    申请人： Hiroshi Segawa ,  Satoshi Kumaki ,  Yoshinori Matsuura

    发明人： Hiroshi Segawa ,  Satoshi Kumaki ,  Yoshinori Matsuura

    IPC分类号： H04N19/50 ,  H03M7/30 ,  H04N19/102 ,  H04N19/146 ,  H04N19/423 ,  H04N19/70 ,  H04N7/12

    CPC分类号： H04N19/152 ,  H04N19/132 ,  H04N19/159 ,  H04N19/172 ,  H04N19/46 ,  H04N19/61

    摘要： To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (7A) executes a picture top detection processing for discarding image compression data (S2) until a top of a picture of the image compression data (S2) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor (5) brings a detection start register (8) into a set state and causes the picture top detector (7A) to execute the picture top detection processing during an overflow of an output buffer (3a), and executes an interruption processing of rewriting, as a value of a write address register (9), an address where a top of an overflow picture to be a picture causing the overflow is stored.

    摘要翻译： 提供一种能够最小化在输出缓冲器溢出期间在再现图像上引起的图像质量劣化的图像压缩编码装置和方法。 图像顶部检测器（7A）执行用于丢弃图像压缩数据（S2）的图像顶部检测处理，直到在检测到开始地址期间检测到图像压缩数据（S 2）的图像的顶部，并重新开始 检测到图像顶部后的正常操作。 处理器（5）使检测开始寄存器（8）进入设置状态，并使图像顶部检测器（7A）在输出缓冲器（3a）溢出期间执行图像顶部检测处理，并执行中断 作为写入地址寄存器（9）的值的重写处理，存储溢出图像的顶部作为导致溢出的图像的地址。

    Data multiplexing device multiplexing transport stream generated from encoded data
    8.
    发明授权
    Data multiplexing device multiplexing transport stream generated from encoded data 有权
    数据复用设备复用从编码数据生成的传输流

    公开(公告)号：US06792006B1

    公开(公告)日：2004-09-14

    申请号：US09604006

    申请日：2000-06-26

    申请人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Hiroshi Segawa

    发明人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Hiroshi Segawa

    IPC分类号： H04J302

    CPC分类号： H04N7/52 ,  H04J3/22 ,  H04N21/23611 ,  H04N21/2362 ,  H04N21/2368 ,  H04N21/2389 ,  H04N21/4385

    摘要： The data multiplexing device includes a header information memory storing header information, ES buffers holding encoded data of a plurality of media, an output buffer holding packetized data, and a transfer controlling unit controlling a transfer of the header information stored in the header information memory and the encoded data held in the ES buffers and writing into the output buffer as the packetized data. The transfer controlling unit can generate the packetized data simply by controlling the transfer of the header information stored in the header information memory and the encoded data held in the ES buffers, whereby the media multiplexing can be readily achieved.

    摘要翻译： 数据多路复用装置包括存储标题信息的头信息存储器，保存多个媒体的编码数据的ES缓冲器，保持分组化数据的输出缓冲器和控制存储在标题信息存储器中的标题信息的传送的传送控制单元， 编码数据保存在ES缓冲器中并作为分组化数据写入输出缓冲器。 转移控制单元可以简单地通过控制存储在标题信息存储器中的报头信息的传送和保存在ES缓冲器中的编码数据来简单地生成分组数据，从而可以容易地实现媒体复用。

    Semiconductor integrated circuit device having a memory and an operational unit integrated therein
    9.
    发明授权
    Semiconductor integrated circuit device having a memory and an operational unit integrated therein 失效
    具有集成在其中的存储器和操作单元的半导体集成电路器件

    公开(公告)号：US5379257A

    公开(公告)日：1995-01-03

    申请号：US767767

    申请日：1991-09-30

    申请人： Tetsuya Matsumura ,  Hiroshi Segawa ,  Kazuya Ishihara ,  Shinichi Uramoto ,  Masahiko Yoshimoto

    发明人： Tetsuya Matsumura ,  Hiroshi Segawa ,  Kazuya Ishihara ,  Shinichi Uramoto ,  Masahiko Yoshimoto

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C13/00

    CPC分类号： G11C7/1006 ,  G11C2207/104

    摘要： A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays. Each operational circuit effects the predetermined operation on the data read from the two bit arrays in the corresponding subarray. Each bit array has selectors responsive to external addresses to select one column from each bit array and connect this column to a corresponding operational circuit.

    摘要翻译： 半导体集成电路装置包括用于存储要处理的数据的存储单元阵列和用于对从存储单元阵列读取的数据进行预定操作的操作单元。 存储单元阵列具有用于存储第一和第二组的第一和第二数据字的第一和第二区域。 第一数据字和第二数据字各自包括多个数据位。 第一区域包括用于存储第一数据字中相同数位的数据位的多个位阵列，并且第二区域包括用于存储第二数据字中相同数字的数据位的多个位数组。 第一组和第二组的位阵列以数据字的数位顺序交替排列。 存储相同数位数据位的位数组形成一个子阵列。 一个数据字中的数据位存储在位阵列的相同位置。 操作单元包括各自对应于一个子阵列的操作电路。 每个操作电路对从相应子阵列中的两个位阵列读取的数据执行预定的操作。 每个位阵列具有响应于外部地址的选择器，从每个位阵列中选择一个列，并将该列连接到相应的运算电路。

    Read only memory for storing multi-data
    10.
    发明授权
    Read only memory for storing multi-data 失效
    只读存储器用于存储多数据

    公开(公告)号：US5394355A

    公开(公告)日：1995-02-28

    申请号：US109509

    申请日：1993-08-20

    申请人： Shinichi Uramoto ,  Tetsuya Matsumura ,  Masahiko Yoshimoto ,  Kazuya Ishihara ,  Hiroshi Segawa

    发明人： Shinichi Uramoto ,  Tetsuya Matsumura ,  Masahiko Yoshimoto ,  Kazuya Ishihara ,  Hiroshi Segawa

    IPC分类号： G11C11/56 ,  G11C17/00

    CPC分类号： G11C11/56 ,  G11C11/5692 ,  G11C2211/5617 ,  G11C2211/5634

    摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

    摘要翻译： 只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。 存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。 通过切换参考电位传输线的电位来改变存储单元中的存储数据。 这使得能够将不同的数据位存储在一个存储单元中。