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    Voltage generating circuit capable of supplying stable output voltage regardless of external input voltage
    2.
    发明授权
    Voltage generating circuit capable of supplying stable output voltage regardless of external input voltage 失效
    电压发生电路，无论外部输入电压如何，均能提供稳定的输出电压

    公开(公告)号：US06980048B2

    公开(公告)日：2005-12-27

    申请号：US10384557

    申请日：2003-03-11

    Applicant: Kee-won Kwon

    Inventor： Kee-won Kwon

    IPC: G11C5/14 ,  G05F1/565 ,  G05F1/56 ,  H03L5/00

    CPC classification number: G05F1/565

    Abstract: A voltage generating circuit capable of generating a stable output voltage irrespective of a variation in external voltage. The voltage generating circuit includes a voltage comparing circuit that operates in response to an activation signal and outputs output voltage to a control node in response to a difference between a reference voltage and an internal voltage; an internal voltage control circuit that is connected to the control node, and receives the external voltage and controls the level of the internal voltage, which is applied to a load, in response to a voltage value of the control node, and an adjusting means for adjusting an amount of driving current flowing through the internal voltage control circuit by controlling the voltage level at the control node. The adjusting means may include any combination of a clamp circuit, a voltage compensating circuit, and a voltage drop circuit.

    Abstract translation: 一种电压产生电路，能够产生稳定的输出电压，而与外部电压的变化无关。 电压产生电路包括响应于激活信号而工作的电压比较电路，并响应于参考电压和内部电压之间的差异将输出电压输出到控制节点; 内部电压控制电路，其连接到所述控制节点，并且响应于所述控制节点的电压值接收所述外部电压并且控制施加到负载的内部电压的电平;以及调整装置， 通过控制控制节点处的电压电平来调节流过内部电压控制电路的驱动电流的量。 调整装置可以包括钳位电路，电压补偿电路和电压降电路的任何组合。

    Output drivers having adjustable swing widths during test mode operation
    3.
    发明申请
    Output drivers having adjustable swing widths during test mode operation 有权
    输出驱动器在测试模式操作期间具有可调整的摆幅宽度

    公开(公告)号：US20050218934A1

    公开(公告)日：2005-10-06

    申请号：US11098818

    申请日：2005-04-05

    Applicant: Seung-hoon Lee ,  Kee-won Kwon ,  Jung-hwan Choi

    Inventor： Seung-hoon Lee ,  Kee-won Kwon ,  Jung-hwan Choi

    IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02

    CPC classification number: H03K19/018585

    Abstract: An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.

    Abstract translation: 输出驱动器响应于输入信号和摆幅控制信号（TE）。 输出驱动器被配置为当摆幅控制信号指定正常操作模式和第二摆幅宽度（例如，轨至轨）时，产生具有第一摆动宽度（例如，小于轨至轨）的输出信号， 摇摆宽度控制信号指定测试操作模式时。

    Non-volatile memory device and method of operating the same
    5.
    发明申请
    Non-volatile memory device and method of operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20080316824A1

    公开(公告)日：2008-12-25

    申请号：US12071349

    申请日：2008-02-20

    Applicant: Ju-hee Park ,  Jae-wong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    Inventor： Ju-hee Park ,  Jae-wong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    IPC: G11C16/06 ,  G11C16/04

    CPC classification number: G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

    Abstract: Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

    Abstract translation: 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

    Output drivers having adjustable swing widths during test mode operation
    6.
    发明授权
    Output drivers having adjustable swing widths during test mode operation 有权
    输出驱动器在测试模式操作期间具有可调整的摆幅宽度

    公开(公告)号：US07259592B2

    公开(公告)日：2007-08-21

    申请号：US11098818

    申请日：2005-04-05

    Applicant: Seung-hoon Lee ,  Kee-won Kwon ,  Jung-hwan Choi

    Inventor： Seung-hoon Lee ,  Kee-won Kwon ,  Jung-hwan Choi

    IPC: H03K19/094 ,  H03K5/22

    CPC classification number: H03K19/018585

    Abstract: An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.

    Abstract translation: 输出驱动器响应于输入信号和摆幅控制信号（TE）。 输出驱动器被配置为当摆幅控制信号指定正常操作模式和第二摆幅宽度（例如，轨至轨）时，产生具有第一摆动宽度（例如，小于轨至轨）的输出信号， 摇摆宽度控制信号指定测试操作模式时。

    Non-volatile memory device including block state confirmation cell and method of operating the same
    7.
    发明申请
    Non-volatile memory device including block state confirmation cell and method of operating the same 审中-公开
    包括块状态确认单元的非易失性存储器件及其操作方法

    公开(公告)号：US20120026790A1

    公开(公告)日：2012-02-02

    申请号：US13137668

    申请日：2011-09-01

    Applicant: Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    Inventor： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    IPC: G11C16/10 ,  G11C16/06 ,  G11C16/04

    CPC classification number: G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

    Abstract: Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

    Abstract translation: 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

    Stacked memory device and method thereof
    8.
    发明申请
    Stacked memory device and method thereof 有权
    堆叠式存储器件及其方法

    公开(公告)号：US20100091541A1

    公开(公告)日：2010-04-15

    申请号：US12588275

    申请日：2009-10-09

    Applicant: Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    Inventor： Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    IPC: G11C5/02 ,  G11C8/10 ,  G11C11/00 ,  G11C7/00

    CPC classification number: G11C5/02 ,  G11C5/143 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71

    Abstract: A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

    Abstract translation: 堆叠存储器件包括多个存储器层，其中多个存储器层中的至少一个堆叠在多个存储器层中的另一个上，并且每个存储器层包括存储器单元阵列，第一有源电路单元配置 将至少一个存储器单元的地址信息分类并处理为垂直地址信息和水平地址信息，以及至少一个第二有源电路单元，配置为基于处理的信号为存储器单元中的至少一个生成存储器选择信号 由第一有源电路单元。

    Dynamic random access memory device and associated refresh cycle
    9.
    发明授权
    Dynamic random access memory device and associated refresh cycle 失效
    动态随机存取存储器件和相关刷新周期

    公开(公告)号：US07477563B2

    公开(公告)日：2009-01-13

    申请号：US11604708

    申请日：2006-11-28

    Applicant: Uk-song Kang ,  Kee-won Kwon

    Inventor： Uk-song Kang ,  Kee-won Kwon

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/408 ,  G11C2207/104 ,  G11C2211/4061

    Abstract: A dynamic random access memory device having reduced power consumption and a refresh cycle method. The memory device includes a monitoring address storage unit storing multiple monitoring addresses, an error correction code (ECC) engine detecting whether or not an error occurs in monitoring bits corresponding to the monitoring addresses, and a refresh cycle determining circuit adjusting a self refresh cycle depending on whether or not an error occurs in the monitoring bits.

    Abstract translation: 具有降低功耗的动态随机存取存储器件和刷新循环方法。 存储装置包括存储多个监视地址的监视地址存储单元，检测在与监视地址相对应的监视位中是否发生错误的纠错码（ECC）引擎，以及刷新周期确定电路，其根据 关于监视位中是否发生错误。

    Semiconductor memory device comprising memory having active restoration function
    10.
    发明授权
    Semiconductor memory device comprising memory having active restoration function 失效
    半导体存储器件包括具有主动恢复功能的存储器

    公开(公告)号：US06882561B2

    公开(公告)日：2005-04-19

    申请号：US10649850

    申请日：2003-08-26

    Applicant: Kee-won Kwon ,  Su-jin Ahn

    Inventor： Kee-won Kwon ,  Su-jin Ahn

    IPC: G11C7/00 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/24

    CPC classification number: G11C11/405 ,  G11C11/404 ,  G11C11/4091

    Abstract: A semiconductor memory device includes a sense line, a data line, a memory connected between the sense line and the data line having an active restoration function, and a sense amplifier connected between the sense line and the data line. The sense amplifier senses and inverts the data in the sense line, and outputs the inverted data to the data line. The polarity of the data on the sense line is opposite the polarity of the data on the data line, and the data in the data line are written to the memory. The semiconductor memory device is capable of performing an active restoration function which makes it possible to rewrite the result of sensing operations from the sense amplifier without the need for an additional circuit or operations.

    Abstract translation: 半导体存储器件包括检测线，数据线，连接在感测线和具有有效恢复功能的数据线之间的存储器，以及连接在检测线和数据线之间的读出放大器。 感测放大器感测并反转感测线中的数据，并将反相数据输出到数据线。 感测线上的数据的极性与数据线上的数据的极性相反，数据线中的数据被写入存储器。 半导体存储器件能够执行主动恢复功能，其使得可以从感测放大器重写感测操作的结果，而不需要额外的电路或操作。

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