公开(公告)号：US20130249615A1

公开(公告)日：2013-09-26

申请号：US13616606

申请日：2012-09-14

申请人： Kelvin Yi-Tse LAI ,  Chen-Yi LEE

发明人： Kelvin Yi-Tse LAI ,  Chen-Yi LEE

IPC分类号： H03K3/017

CPC分类号： G01R23/15 ,  G01D5/243 ,  G01P15/125 ,  G01P21/00 ,  G01R23/10 ,  G01R25/08 ,  G01R29/023 ,  G01R29/027

摘要： A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width as sociated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.

摘要翻译： 数字感测装置包括能够提供与环境参数相关联的感测响应的感测单元和包括用于产生具有与感测响应相关的脉冲宽度的脉冲信号的读取单元的数字读出模块和转换单元。 转换单元包括用于产生可变频率时钟信号的时钟信号发生器和可用于使用时钟信号对脉冲信号的脉冲宽度的宽度值进行计数的计数器，以便产生数字感测代码。 来自时钟信号发生器的时钟信号的频率可调，以调节脉冲信号脉冲宽度宽度值的分辨率。

公开(公告)号：US20120322253A1

公开(公告)日：2012-12-20

申请号：US13595599

申请日：2012-08-27

申请人： Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

发明人： Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

IPC分类号： H01L21/283 ,  H01L21/311

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

摘要翻译： 该描述涉及包括在半导体衬底上形成界面层的方法。 该方法还包括蚀刻回界面层。 该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层 至700℃。该方法还包括在界面层上沉积高k电介质材料。

公开(公告)号：US20110302045A1

公开(公告)日：2011-12-08

申请号：US13151360

申请日：2011-06-02

申请人： Chen-Yi LEE ,  Ching-Yao Huang ,  Chih-Hua Chang ,  Chih-Wei Wu ,  I-Ju Wu ,  Hsin-Chuh Lu ,  Ya-Hui Lee ,  Yi-Wen Chen ,  Ju-Chuan Chien

发明人： Chen-Yi LEE ,  Ching-Yao Huang ,  Chih-Hua Chang ,  Chih-Wei Wu ,  I-Ju Wu ,  Hsin-Chuh Lu ,  Ya-Hui Lee ,  Yi-Wen Chen ,  Ju-Chuan Chien

IPC分类号： G06Q30/00

CPC分类号： G06Q30/08 ,  G06F2216/11 ,  G06Q10/10 ,  G06Q30/0605

摘要： The invention discloses an automatic patent transaction system. The invention comprises a patent database, a member database, a match computing device, a share computing device, a non-member database, and a licensing and transacting computing device. The operation method of the invention also comprises a method for the participation of member and non-member, and a method for the participation of member only. Thus, the invention is able to increase the trade efficiency of the patent and reduce the trade cost of the patent.

摘要翻译： 本发明公开了一种自动专利交易系统。 本发明包括专利数据库，成员数据库，匹配计算设备，共享计算设备，非成员数据库以及许可和交易计算设备。 本发明的操作方法还包括成员和非成员参与的方法以及仅参加成员的方法。 因此，本发明能够提高专利的贸易效率并降低专利的交易成本。

公开(公告)号：US20130038369A1

公开(公告)日：2013-02-14

申请号：US13352350

申请日：2012-01-18

申请人： Chen-Yi LEE ,  Chien-Ying YU ,  Chia-Jung YU

发明人： Chen-Yi LEE ,  Chien-Ying YU ,  Chia-Jung YU

IPC分类号： H03K5/06

CPC分类号： H03L7/0997

摘要： A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.

摘要翻译： 延迟单元包括第一反相晶体管对，第二反相晶体管对和多个延迟单元。 第一反相晶体管对用于接收输入信号。 第二反相晶体管对与第一反相晶体管对电交叉耦合并由第一反相晶体管对交叉控制。 延迟单元在第一反相晶体管对之间和第二反向晶体管对之间级联，从而依次提供多个信号传播延迟，其中输入信号被第一反相晶体管对延迟预定时间，第二 反相晶体管对和延迟单元，从而产生与预定时间对应的输出信号。 提供了包括上述延迟单元的数字控制振荡器。

公开(公告)号：US20220297131A1

公开(公告)日：2022-09-22

申请号：US17540868

申请日：2021-12-02

申请人： Chen-Yi LEE

发明人： Chen-Yi LEE ,  Yun-Sheng CHAN

IPC分类号： B01L7/00 ,  B01L3/00 ,  C12Q3/00 ,  G01N35/00

摘要： A microelectrode device, microfluidic chip, and microfluidic examination method are provided. The microfluidic chip includes a top plate and a microelectrode dot array having several microelectrode devices. Each microelectrode device includes a microfluidic electrode, heating electrode, and control circuit. The control circuit includes a microfluidic control and location sensing circuit, storage circuit, and temperature control circuit. The microfluidic control and location sensing circuit moves a sample within an enabling period of a microfluidic control signal and detects a capacitance value between the microfluidic electrode and the top plate within an enabling period of a location control signal. The storage circuit outputs the capacitance value, reads in the sample operation setup, and reads in the heating control setup within different enabling periods of the clock. The temperature control circuit determines either on or off according to the heating control setup within an enabling period of a heating control signal.

公开(公告)号：US20100317184A1

公开(公告)日：2010-12-16

申请号：US12782859

申请日：2010-05-19

申请人： Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

发明人： Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

IPC分类号： H01L21/28

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

摘要翻译： 提供了一种用于降低高k电介质和金属栅极叠层的界面层（IL）厚度的方法。 在一个实施例中，该方法包括在半导体衬底上形成界面层，蚀刻回界面层，在界面层上沉积高k电介质材料，以及在高k电介质材料上形成金属栅极。 IL可以是化学氧化物，臭氧化氧化物，热氧化物，或者由化学氧化物等的紫外线臭氧（UVO）氧化过程形成.II的回蚀可以通过稀释HF（DHF）工艺，蒸汽HF工艺 ，或任何其他合适的过程。 该方法还可以包括在沉积高k介电材料之前在界面层上进行UV固化或低热预算退火。

公开(公告)号：US20090160686A1

公开(公告)日：2009-06-25

申请号：US12178987

申请日：2008-07-24

申请人： Cheng-Chi WONG ,  Yung-Yu LEE ,  Ming-Wei LAI ,  Chien-Ching LIN ,  Hsie-Chia CHANG ,  Chen-Yi LEE

发明人： Cheng-Chi WONG ,  Yung-Yu LEE ,  Ming-Wei LAI ,  Chien-Ching LIN ,  Hsie-Chia CHANG ,  Chen-Yi LEE

IPC分类号： H03M7/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2957 ,  H03M13/6566

摘要： An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention.

摘要翻译： 公开了一种用于迭代网络的多级网络的装置和方法。 该装置具有M级，每级使用N个多路复用器同时发送N个码字分区。 每个起始终端，存储器的输出端口，软入门解码器或多路复用器都具有两条路径，用于在下一级与两个不同的多路复用器耦合。 一条路径将源连接到一个多路复用器的第一个数据端口; 另一个将源连接到另一个多路复用器的第二个数据端口。 两个多路复用器将以相同的1位信号进行控制，因此每个源只有一条到下一级的有效路径。 本发明可以保证N个数据块的传输没有争用。

公开(公告)号：US20220297120A1

公开(公告)日：2022-09-22

申请号：US17695515

申请日：2022-03-15

申请人： Chen-Yi LEE

发明人： Chen-Yi LEE ,  Yun-Sheng CHAN

IPC分类号： B01L3/00

摘要： A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.

公开(公告)号：US20120159187A1

公开(公告)日：2012-06-21

申请号：US13034713

申请日：2011-02-25

申请人： Po-Chun LIU ,  Hsie-Chia CHANG ,  Chen-Yi LEE

发明人： Po-Chun LIU ,  Hsie-Chia CHANG ,  Chen-Yi LEE

IPC分类号： G06F12/14

CPC分类号： G06F21/755

摘要： An electronic device and a method for protecting against a differential power analysis attack are disclosed herein. The electronic device includes an encryption/decryption unit, a random number generator and a countermeasure circuit. The encryption/decryption unit can provide an enable signal when encrypting or decrypting more bits of data. The random number generator can generate random data. When receiving the enable signal, the countermeasure circuit can operate according to the bits of data and the random data.

摘要翻译： 本文公开了一种用于防止差分功率分析攻击的电子设备和方法。 电子设备包括加密/解密单元，随机数发生器和对策电路。 加密/解密单元可以在加密或解密更多数据位时提供使能信号。 随机数生成器可以生成随机数据。 当接收到使能信号时，对策电路可以根据数据位和随机数据进行操作。

公开(公告)号：US20110296281A1

公开(公告)日：2011-12-01

申请号：US12790875

申请日：2010-05-31

申请人： Yi-Min LIN ,  Chi-Heng YANG ,  Hsie-Chia CHANG ,  Chen-Yi LEE

发明人： Yi-Min LIN ,  Chi-Heng YANG ,  Hsie-Chia CHANG ,  Chen-Yi LEE

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/158 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6561

摘要： An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

摘要翻译： 本文公开了一种处理循环码的装置和方法，其中装置包括至少一个可重新配置模块和编码器控制器。 可重构模块包括多个线性反馈移位寄存器。 编码器控制器可以控制可重构模块将生成多项式归因于阶乘多项式。 在可重构模块中，线性反馈移位寄存器可分别注册多项因子多项式。