公开(公告)号：US20130148408A1

公开(公告)日：2013-06-13

申请号：US13704649

申请日：2012-08-09

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Yoshikazu Katoh

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Yoshikazu Katoh

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/79

摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.

摘要翻译： 一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时， 非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度 电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。

公开(公告)号：US08867259B2

公开(公告)日：2014-10-21

申请号：US13704649

申请日：2012-08-09

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh ,  Shunsaku Muraoka

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh ,  Shunsaku Muraoka

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/79

摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.

摘要翻译： 一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时， 非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度 电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。

公开(公告)号：US08675387B2

公开(公告)日：2014-03-18

申请号：US13121262

申请日：2010-07-26

申请人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Yoshikazu Katoh

发明人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Yoshikazu Katoh

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0002 ,  G11C13/0069 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

摘要： A variable resistance nonvolatile memory device includes a plurality of memory cells in each of which a variable resistance element and a current steering element having two terminals are connected in series. Additionally, a current limit circuit limits a first current flowing in a direction for changing the memory cells to a low resistance state, and a boost circuit increases, when one of the memory cells changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.

摘要翻译： 可变电阻非易失性存储器件包括多个存储单元，每个存储单元中的每一个具有两个端子的可变电阻元件和电流控制元件串联连接。 此外，电流限制电路限制在用于将存储单元改变为低电阻状态的方向上流动的第一电流，并且当一个存储单元变为低电阻状态时，升压电路增加第一电流 在存储单元变为低电阻状态之前的周期。

公开(公告)号：US20110182109A1

公开(公告)日：2011-07-28

申请号：US13121262

申请日：2010-07-26

申请人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Yoshikazu Katoh

发明人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Yoshikazu Katoh

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C13/0069 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

摘要： A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are connected in series; a current limit circuit (105b) which limits a first current flowing in a direction for changing the memory cells (M11, M12, M21, M22) to a low resistance state; and a boost circuit (105d) which increases, when one of the memory cells (M11, M12, M21, M22) changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.

摘要翻译： 根据本发明的一个方面的可变电阻非易失性存储器件（100）包括：多个存储单元（M11，M12，M21，M22），其中可变电阻元件（R11，R12，R21，R22） 并且具有两个端子的电流控制元件（D11，D12，D21，D22）串联连接; 电流限制电路（105b），限制在用于将存储单元（M11，M12，M21，M22）改变的方向上流动的第一电流为低电阻状态; 以及升压电路（105d），当存储单元（M11，M12，M21，M22）中的一个变为低电阻状态时，在存储单元变为低电阻状态之前的第一周期内增加第一电流。

公开(公告)号：US08902629B2

公开(公告)日：2014-12-02

申请号：US13511275

申请日：2011-09-28

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Shunsaku Muraoka

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Shunsaku Muraoka

IPC分类号： G11C11/00 ,  H01L45/00 ,  H01L27/10 ,  H01L27/24 ,  G11C13/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.

摘要翻译： 在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。 当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。 如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。 由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

公开(公告)号：US08305795B2

公开(公告)日：2012-11-06

申请号：US12999019

申请日：2010-04-27

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).

摘要翻译： 为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。 在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻 州（401）。

公开(公告)号：US08325508B2

公开(公告)日：2012-12-04

申请号：US13001905

申请日：2010-06-08

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/79

摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).

摘要翻译： 提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。 对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。 写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。 在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有 最大电阻值。 在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻 元件从低电阻状态（S52）到高电阻状态（S53）。

公开(公告)号：US20120230085A1

公开(公告)日：2012-09-13

申请号：US13511275

申请日：2011-09-28

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Shunsaku Muraoka

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Shunsaku Muraoka

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.

摘要翻译： 在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。 当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。 如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。 由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

公开(公告)号：US20120120712A1

公开(公告)日：2012-05-17

申请号：US13001943

申请日：2010-06-04

申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/00 ,  H01L21/8239

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

摘要： An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not a current resistance value of the variable resistance element (100) is lower than a resistance value in a high resistance state; and a voltage application step (S36) of applying a voltage pulse having a voltage not exceeding a sum of a forming voltage and a forming margin when the determination is made that the current resistance value is not lower than the resistance value in the high resistance state (No at S35). The determination step (S35) and the voltage application step (S36) are repeated to process all memory cells in a memory array (202) (S34 to S37).

摘要翻译： 提供了一种用于对可变电阻元件进行成形以最大化可变电阻元件的操作窗口的最佳形成方法。 成形方法用于初始化可变电阻元件（100）。 形成方法包括：确定可变电阻元件（100）的当前电阻值是否低于高电阻状态下的电阻值的确定步骤（S35） 以及当确定当前电阻值不低于高电阻状态下的电阻值时，施加具有不超过形成电压和形成余量之和的电压的电压脉冲的电压施加步骤（S36） （S35否）。 重复确定步骤（S35）和电压施加步骤（S36）以处理存储器阵列（202）中的所有存储器单元（S34至S37）。

公开(公告)号：US08665633B2

公开(公告)日：2014-03-04

申请号：US13599406

申请日：2012-08-30

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： A method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step, thereby setting the variable resistance element through the low resistance state to the high resistance state.

摘要翻译： 根据施加电压的极性将数据写入可变电阻元件（10a）的方法，该可变电阻元件（10a）根据施加的电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为对上电极（11）相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件设置为低电阻状态（403,402）; 并且在低电阻写入步骤中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件通过低电阻状态设置为高电阻状态。