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公开(公告)号：US08867259B2
公开(公告)日：2014-10-21
申请号：US13704649
申请日：2012-08-09
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.
摘要翻译： 一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时， 非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度 电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。
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公开(公告)号：US20130148408A1
公开(公告)日：2013-06-13
申请号：US13704649
申请日：2012-08-09
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.
摘要翻译： 一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时， 非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度 电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。
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3.发明授权Variable resistance nonvolatile memory device and programming method for same 有权可变电阻非易失性存储器件及其编程方法相同公开(公告)号：US08675387B2
公开(公告)日：2014-03-18
申请号：US13121262
申请日：2010-07-26
CPC分类号： G11C13/0002 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile memory device includes a plurality of memory cells in each of which a variable resistance element and a current steering element having two terminals are connected in series. Additionally, a current limit circuit limits a first current flowing in a direction for changing the memory cells to a low resistance state, and a boost circuit increases, when one of the memory cells changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
摘要翻译： 可变电阻非易失性存储器件包括多个存储单元，每个存储单元中的每一个具有两个端子的可变电阻元件和电流控制元件串联连接。 此外，电流限制电路限制在用于将存储单元改变为低电阻状态的方向上流动的第一电流，并且当一个存储单元变为低电阻状态时，升压电路增加第一电流 在存储单元变为低电阻状态之前的周期。
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4.发明申请公开(公告)号：US20110182109A1
公开(公告)日：2011-07-28
申请号：US13121262
申请日：2010-07-26
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0069 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are connected in series; a current limit circuit (105b) which limits a first current flowing in a direction for changing the memory cells (M11, M12, M21, M22) to a low resistance state; and a boost circuit (105d) which increases, when one of the memory cells (M11, M12, M21, M22) changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.
摘要翻译： 根据本发明的一个方面的可变电阻非易失性存储器件（100）包括：多个存储单元（M11，M12，M21，M22），其中可变电阻元件（R11，R12，R21，R22） 并且具有两个端子的电流控制元件（D11，D12，D21，D22）串联连接; 电流限制电路（105b），限制在用于将存储单元（M11，M12，M21，M22）改变的方向上流动的第一电流为低电阻状态; 以及升压电路（105d），当存储单元（M11，M12，M21，M22）中的一个变为低电阻状态时，在存储单元变为低电阻状态之前的第一周期内增加第一电流。
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5.发明授权Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device 有权可变电阻非易失性存储元件写入方法和可变电阻非易失性存储器件公开(公告)号：US09378817B2
公开(公告)日：2016-06-28
申请号：US13581925
申请日：2012-03-22
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092
摘要： A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.
摘要翻译： 一种可变电阻非易失性存储元件写入方法，通过向包括可变电阻元件的存储单元施加电压脉冲，根据所施加的电压脉冲的极性可逆地改变第一电阻状态和第二电阻状态之间的可变电阻元件 被提供。 可变电阻非易失性存储元件写入方法包括施加第一初步电压脉冲，并随后将第一电压脉冲施加到可变电阻元件，以将可变电阻元件从第二电阻状态改变到第一电阻状态，第一初步电压脉冲为 电压绝对值比第二阈值电压小，并且极性与第一电压脉冲不同。
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6.发明申请VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT WRITING METHOD AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权可变电阻非易失性存储器元件写入方法和可变电阻非易失性存储器件公开(公告)号：US20140078811A1
公开(公告)日：2014-03-20
申请号：US13990209
申请日：2012-11-21
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Yuichiro Ikeda
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/00 , G11C13/004 , G11C13/0064 , G11C2013/0073 , G11C2013/0092
摘要： Provided is a method of writing to a variable resistance nonvolatile memory element which is capable of both improving retention characteristics and enlarging a window of operation. In the method of writing, to write “1” data (LR), first a weak HR writing process is performed in which a weak HR writing voltage pulse set for changing the variable resistance nonvolatile memory element to an intermediate resistance state is applied and, subsequently, a LR writing process is performed in which a LR writing voltage pulse set for changing the variable resistance nonvolatile memory element from the intermediate resistance state to a LR state is applied.
摘要翻译： 提供一种写入能够改善保持特性和扩大操作窗口的可变电阻非易失性存储元件的方法。 在写入方法中，为了写入“1”数据（LR），首先执行将用于将可变电阻非易失性存储元件变更为中间电阻状态而设定的弱的HR写入电压脉冲的弱的HR写入处理， 随后，执行LR写入处理，其中设置用于将可变电阻非易失性存储元件从中间电阻状态改变为LR状态的LR写入电压脉冲。
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7.发明申请VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT WRITING METHOD AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权可变电阻非易失性存储器元件写入方法和可变电阻非易失性存储器件公开(公告)号：US20130188414A1
公开(公告)日：2013-07-25
申请号：US13581925
申请日：2012-03-22
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092
摘要： A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.
摘要翻译： 一种可变电阻非易失性存储元件写入方法，通过向包括可变电阻元件的存储单元施加电压脉冲，根据所施加的电压脉冲的极性可逆地改变第一电阻状态和第二电阻状态之间的可变电阻元件 被提供。 可变电阻非易失性存储元件写入方法包括施加第一初步电压脉冲，并随后将第一电压脉冲施加到可变电阻元件，以将可变电阻元件从第二电阻状态改变到第一电阻状态，第一初步电压脉冲为 电压绝对值比第二阈值电压小，并且极性与第一电压脉冲不同。
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8.发明申请NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY DEVICE 有权非易失性存储器件和将数据写入非易失性存储器件的方法公开(公告)号：US20110128776A1
公开(公告)日：2011-06-02
申请号：US13056925
申请日：2010-05-14
CPC分类号： G11C13/0069 , G11C11/14 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0038 , G11C2013/0073 , G11C2013/009 , G11C2213/15 , G11C2213/34 , G11C2213/79 , G11C2213/82
摘要： A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to a first resistance state (RH) in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a second voltage (V2) which is a positive voltage which is equal in absolute value to the first voltage, the resistance variable layer changes to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage (V3) higher than the second voltage, when the interelectrode voltage reaches the third voltage, and the resistance variable layer changes to the first resistance state in such a manner that its resistance value stops increasing when the interelectrode current reaches a first current (Ilim) in a state where the interelectrode voltage is not lower than the second voltage and lower than the third voltage, and the load resistor has a characteristic in which when the electric pulse application device outputs an electric pulse of a second application voltage (VP2), a current flowing by applying to the load resistor, a voltage obtained by subtracting the third voltage from the second application voltage, is not higher than a first current value.
摘要翻译： 电阻变化层具有电阻变化层变为第二电阻状态（RL）的特性，使得当电极间电压达到作为负电压的第一电压（V1）时，其电阻值停止减小， 电阻变化层以这样的方式改变为第一电阻状态（RH），使得当电极间电压达到作为与第一电压的绝对值相等的正电压的第二电压（V2）时，其电阻值开始增加， 电阻变化层以这样的方式变化为电阻变化层流动电极间电流，使得当电极间电压达到第三电压时，电极间电压保持在高于第二电压的第三电压（V3） ，并且电阻变化层以其电阻值停止增加的方式变为第一电阻状态 当所述电极间电流在所述电极间电压不低于所述第二电压且低于所述第三电压的状态下达到第一电流（Ilim）时，并且所述负载电阻器具有当所述电脉冲施加装置输出 第二施加电压（VP2）的电脉冲，通过施加到负载电阻器流动的电流，从第二施加电压减去第三电压获得的电压不高于第一电流值。
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9.发明授权Nonvolatile memory device and method of writing data to nonvolatile memory device 有权非易失性存储器件和将数据写入非易失性存储器件的方法公开(公告)号：US08406035B2
公开(公告)日：2013-03-26
申请号：US13056925
申请日：2010-05-14
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/14 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0038 , G11C2013/0073 , G11C2013/009 , G11C2213/15 , G11C2213/34 , G11C2213/79 , G11C2213/82
摘要： A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to a first resistance state (RH) in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a second voltage (V2) which is a positive voltage which is equal in absolute value to the first voltage, the resistance variable layer changes to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage (V3) higher than the second voltage, when the interelectrode voltage reaches the third voltage, and the resistance variable layer changes to the first resistance state in such a manner that its resistance value stops increasing when the interelectrode current reaches a first current (Ilim) in a state where the interelectrode voltage is not lower than the second voltage and lower than the third voltage, and the load resistor has a characteristic in which when the electric pulse application device outputs an electric pulse of a second application voltage (VP2), a current flowing by applying to the load resistor, a voltage obtained by subtracting the third voltage from the second application voltage, is not higher than a first current value.
摘要翻译： 电阻变化层具有电阻变化层变为第二电阻状态（RL）的特性，使得当电极间电压达到作为负电压的第一电压（V1）时，其电阻值停止减小， 电阻变化层以这样的方式改变为第一电阻状态（RH），使得当电极间电压达到作为与第一电压的绝对值相等的正电压的第二电压（V2）时，其电阻值开始增加， 电阻变化层以这样的方式变化为电阻变化层流动电极间电流，使得当电极间电压达到第三电压时，电极间电压保持在高于第二电压的第三电压（V3） ，并且电阻变化层以其电阻值停止增加的方式变为第一电阻状态 当所述电极间电流在所述电极间电压不低于所述第二电压且低于所述第三电压的状态下达到第一电流（Ilim）时，并且所述负载电阻器具有当所述电脉冲施加装置输出 第二施加电压（VP2）的电脉冲，通过施加到负载电阻器流动的电流，从第二施加电压减去第三电压获得的电压不高于第一电流值。
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公开(公告)号：US20100046270A1
公开(公告)日：2010-02-25
申请号：US12514025
申请日：2007-11-16
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.
摘要翻译： 本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定 单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位 在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大 在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。
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