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    Non-volatile semiconductor storage device and method for manufacturing the same
    4.
    发明授权
    Non-volatile semiconductor storage device and method for manufacturing the same 失效
    非易失性半导体存储装置及其制造方法

    公开(公告)号：US07737486B2

    公开(公告)日：2010-06-15

    申请号：US11859142

    申请日：2007-09-21

    申请人： Masumi Saitoh ,  Ken Uchida

    发明人： Masumi Saitoh ,  Ken Uchida

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/165 ,  H01L29/7881

    摘要： A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

    摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 源极区域和漏极区域，形成在半导体衬底中以便彼此分离; 在所述半导体衬底上形成在所述源极区域和所述漏极区域之间的第一绝缘膜; 形成在所述第一绝缘膜上并具有延伸应变的半导体导电材料层的浮动电极; 形成在浮置电极上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制电极。 浮动电极的延伸应变随着位置从第二绝缘膜向第一绝缘膜前进而逐渐变小，浮动电极在浮动电极和第二绝缘膜之间的界面具有0.01％以上的延伸应变， 并且在浮动电极和第一绝缘膜之间的界面处具有小于0.01％的延伸应变。

    Semiconductor device with negative differential resistance characteristics
    5.
    发明授权
    Semiconductor device with negative differential resistance characteristics 失效
    具有负差分电阻特性的半导体器件

    公开(公告)号：US06690030B2

    公开(公告)日：2004-02-10

    申请号：US09798923

    申请日：2001-03-06

    申请人： Junji Koga ,  Ken Uchida ,  Ryuji Ohba ,  Akira Toriumi

    发明人： Junji Koga ,  Ken Uchida ,  Ryuji Ohba ,  Akira Toriumi

    IPC分类号： H01L2940

    CPC分类号： H01L27/1104 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/7881

    摘要： A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.

    摘要翻译： 形成在硅衬底表面上的栅极氧化膜的厚度部分地减小或者在其源区域上的指定部分“薄化”。 在栅极区域中，以层叠的顺序形成包括p型导电体的第一多晶硅或“多晶硅”膜，隧道氧化物膜和第二p型多晶硅膜的多层结构。 源极区域和第一多晶硅膜构成了高浓度杂质掺杂的pn结，其间铺设有薄的氧化硅膜，提供了也称为Esaki二极管的隧道二极管。 二极管用于负差分电阻。 此外，第一和第二多晶硅膜之间的部分是用作负载的非线性隧道电阻器。 负的差分电阻和负载在低压电源（接地电位）Vss和高压电源Vdd之间串联连接在一起，从而能够形成具有内置双稳态电路的晶体管。 读取用作数据存储节点的第一多晶硅膜的电位信息，并施加晶体管放大。 因此，高速执行数据读取。 同时，在电源之间流动的电流被抑制到较低的电平，从而使等待模式中的功耗最小化。

    Nonvolatile MNOS memory
    7.
    发明授权
    Nonvolatile MNOS memory 失效
    非易失性MNOS存储器

    公开(公告)号：US4630086A

    公开(公告)日：1986-12-16

    申请号：US535233

    申请日：1983-09-23

    申请人： Nobuyuki Sato ,  Kyotake Uchiumi ,  Shinji Nabetani ,  Ken Uchida

    发明人： Nobuyuki Sato ,  Kyotake Uchiumi ,  Shinji Nabetani ,  Ken Uchida

    IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

    CPC分类号： G11C16/0433 ,  G11C16/0466 ,  H01L29/7883

    摘要： A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.

    摘要翻译： 公开了一种非易失性存储器，其具有浮动型EEPROM和MNOS型EEPROM的优点，并且能够以低电压写入和擦除。 非易失性存储器中的每个存储元件具有浮置栅极，控制栅极，半导体主体和浮置栅极之间的栅极绝缘膜，以及控制栅极和浮动栅极之间的层间绝缘膜。 栅极绝缘膜由非常薄的SiO 2膜和形成在其上的薄的Si 3 N 4膜构成。 注入用于存储数据的电荷的电荷重心位于浮动栅极内，而不在Si3N4膜内。

    Pressurized water reactor
    8.
    发明授权
    Pressurized water reactor 有权
    加压水反应堆

    公开(公告)号：US09251919B2

    公开(公告)日：2016-02-02

    申请号：US13993227

    申请日：2011-12-13

    申请人： Chikako Iwaki ,  Tatsumi Ikeda ,  Tetsuzo Yamamoto ,  Masanobu Watanabe ,  Satoru Abe ,  Ken Uchida ,  Hisaki Sato ,  Ken Okuda ,  Kiichi Ito

    发明人： Chikako Iwaki ,  Tatsumi Ikeda ,  Tetsuzo Yamamoto ,  Masanobu Watanabe ,  Satoru Abe ,  Ken Uchida ,  Hisaki Sato ,  Ken Okuda ,  Kiichi Ito

    IPC分类号： G21C13/00 ,  G21C15/02 ,  G21C13/02

    CPC分类号： G21C15/02 ,  G21C5/10 ,  G21C13/02 ,  Y02E30/32

    摘要： The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel (1) to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (1); a cylindrical reactor core barrel (3) which surrounds the fuel assemblies and forms an annular downcomer (6) between the reactor core barrel (3) and the inner surface of the reactor pressure vessel (1); and radial supports. The radial supports are supports which are arranged below the downcomer (6) at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel (3) and the reactor pressure vessel (1). The radial supports each has, for example, a flow path-equipped radial keys (21) and a key groove member (40).

    摘要翻译： 根据一个实施方案的加压水反应器包括：连接入口喷嘴的圆柱形反应器压力容器（1）; 包含在反应堆压力容器（1）内的燃料组件; 围绕燃料组件并在反应堆芯筒（3）和反应堆压力容器（1）的内表面之间形成环形降液管（6）的圆柱形反应堆芯筒（3）; 和径向支撑。 径向支撑件是沿圆周方向间隔地设置在降液管（6）下方的支撑件，每个都具有形成在其中的垂直流动通道，并且将反应堆堆芯筒（3）和反应堆压力容器（1）定位。 径向支撑件各自具有例如具有流动路径的径向键（21）和键槽构件（40）。

    PRESSURIZED WATER REACTOR
    9.
    发明申请
    PRESSURIZED WATER REACTOR 审中-公开
    加压水反应器

    公开(公告)号：US20140037038A1

    公开(公告)日：2014-02-06

    申请号：US13980145

    申请日：2012-01-18

    申请人： Ken Uchida ,  Ken Okuda ,  Kazuyoshi Aoki ,  Hiroshi Ikeda ,  Chikako Iwaki ,  Tetsuzo Yamamoto

    发明人： Ken Uchida ,  Ken Okuda ,  Kazuyoshi Aoki ,  Hiroshi Ikeda ,  Chikako Iwaki ,  Tetsuzo Yamamoto

    IPC分类号： G21C15/02

    CPC分类号： G21C15/02 ,  G21C1/086 ,  Y02E30/32

    摘要： A pressurized water reactor comprises a reactor pressure vessel (11), a cylindrical core barrel (13), a core disposed in the core barrel (13), a lower core support plate (17), and a cylindrical porous plate (31). The core barrel (13) is provided in the reactor pressure vessel (11) and forms, with the inner side surface of the reactor pressure vessel (11), an annular downcomer (14) therebetween. The lower core support plate (17) is provided under the core so as to extend horizontally, and a large number of upward flow holes (80) are formed therein. The cylindrical porous plate (31) demarcates a lower plenum (16) and a bottom part of the downcomer (14), and a plurality of inward flow holes (83) that serve as flow paths from the bottom part of the downcomer (14) to the lower plenum (16) are formed therein. The inward flow holes (83) are inclined upward to the lower plenum (16) on the side on which the inward flow holes are open to the lower plenum (16).

    摘要翻译： 加压水反应器包括反应堆压力容器（11），圆筒形芯筒（13），设置在芯筒（13）中的芯，下芯支撑板（17）和圆柱形多孔板（31）。 芯筒（13）设置在反应堆压力容器（11）中并与反应堆压力容器（11）的内侧表面形成在其间的环形降液管（14）。 下芯体支撑板（17）设置在芯部下方以水平延伸，并且在其中形成大量向上的流动孔（80）。 圆柱形多孔板（31）划分下降管（16）和下降管（14）的底部，以及多个向内流动孔（83），其用作从降液管（14）的底部的流动路径， 到下部通气室（16）。 向内的流通孔（83）向内侧流通孔向下部通气室（16）开放的一侧向下倾斜到下部通气室（16）。

    Semiconductor device and manufacturing method of same
    10.
    发明授权
    Semiconductor device and manufacturing method of same 有权
    半导体器件及其制造方法

    公开(公告)号：US08076231B2

    公开(公告)日：2011-12-13

    申请号：US12401704

    申请日：2009-03-11

    申请人： Masumi Saitoh ,  Ken Uchida

    发明人： Masumi Saitoh ,  Ken Uchida

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

    摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。