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1.发明授权Signal processing circuit for performing a pipelined matrix multiplication upon signals from several linear sensors 失效用于在几个线性传感器信号之间执行管道矩阵多路复用的信号处理电路
公开(公告)号：US5109273A
公开(公告)日：1992-04-28
申请号：US522439
申请日：1990-05-11
摘要： A signal processing circuit operates upon digitized signals from a plurality of linear color sensors that are spatially separated in the page scanning direction by a predetermined number of lines. The digitized signals are realigned in a line rephasing circuit, which provides sets of rephased color values for each scanned element of the original. A matrix multiplication is performed in a row sequential process upon the rephased signals by a group of multipliers, one multiplier for each row coefficient of the matrix. Each multiplier receives a rephased signal and a series of coefficients multiplexed into the circuit from a group of row coefficient registers. By clocking the rephased signals at a submultiple of the coefficient rate, a row-sequential matrix operation is serially performed in a pipelined manner.
摘要翻译： 信号处理电路对来自多个线性颜色传感器的数字化信号进行操作，所述多个线性颜色传感器在页面扫描方向上空间分开预定数量的行。 数字化信号在行重新定标电路中重新对准，它为原始数据的每个扫描元件提供了一组重新分配的颜色值。 通过一组乘法器对重定位信号执行矩阵乘法，对矩阵的每行行系数使用一个乘法器。 每个乘法器从一组行系数寄存器接收一个重新定位的信号和一系列被复用到电路中的系数。 通过以系数速率的倍数计时重新移动的信号，以流水线的方式串行地执行行顺序矩阵运算。
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2.发明授权Method and apparatus for compensating for sensitivity variations in the output of a solid state image sensor 失效用于补偿固态图像传感器输出的灵敏度变化的方法和装置
公开(公告)号：US5086343A
公开(公告)日：1992-02-04
申请号：US522334
申请日：1990-05-11
CPC分类号： H04N1/401 , H04N5/2176
摘要： A correction circuit processes digitized signals from an image sensor and generates gain correction values to compensate for variations in the output of the sensor. While imaging a gain calibration object, the sensor is operated in a calibration mode in which a plurality of calibration values are generated that pertain to each photosite. The digitized calibration values are transformed into log space for processing by a gain level averaging circuit. The log calibration signals are first subtracted from a reference corresponding to a maximum expected signal value. The difference signals are serially accumulated by means of pair of registers and an adder, and the sum is stored in a gain memory. In a subsequent normal operating mode, the summed signals for each photosite are retrieved from the gain memory and bit-shifted to form an average correction value for each photosite. The correction values are applied to an adder in synchronism with sensor signals from like photosites and added therewith in log space to provide gain compensation.
摘要翻译： 校正电路处理来自图像传感器的数字化信号，并且生成增益校正值以补偿传感器的输出的变化。 在对增益校准对象进行成像时，传感器在校准模式下操作，其中生成与每个光子相关的多个校准值。 数字化校准值被变换为对数空间，以便通过增益电平平均电路进行处理。 首先从对应于最大预期信号值的参考中减去对数校准信号。 差分信号通过一对寄存器和一个加法器串行累加，并且该和存储在增益存储器中。 在随后的正常操作模式中，从增益存储器检索每个光子的加和信号并进行位移以形成每个光子的平均校正值。 校正值与来自类似照相机的传感器信号同步地应用于加法器，并将其与对数空间相加，以提供增益补偿。
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3.发明授权Digital correlated double sampling circuit for sampling the output of an image sensor 失效数字相关双采样电路，用于采集图像传感器的输出
公开(公告)号：US5086344A
公开(公告)日：1992-02-04
申请号：US522030
申请日：1990-05-11
CPC分类号： H04N5/2173 , G11C19/285
摘要： A digital correlated double sampling circuit employs three registers and a single clock signal to sample the output of a charge transfer device. The first register samples the reset reference value on the falling edge of the master clock cycle while the remaining two registers sample on the rising edge. The second register samples the image level and the third register samples the output of the first register, thus effecting a delay of the reset reference level. The outputs of the second and third registers, that is, the image level and the reset reference level, are differenced to provide a noise-free image signal.
摘要翻译： 数字相关双采样电路采用三个寄存器和单个时钟信号来对电荷转移装置的输出进行采样。 第一个寄存器在主时钟周期的下降沿采样复位参考值，而其余两个寄存器在上升沿采样。 第二个寄存器采样图像电平，第三个寄存器采样第一个寄存器的输出，从而影响复位参考电平的延迟。 第二和第三寄存器的输出，即图像电平和复位基准电平不同，以提供无噪声的图像信号。
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4.发明授权Real-time digital processor for producing full resolution color signals from a multi-color image sensor 失效用于从多色图像传感器生成全分辨率彩色信号的实时数字处理器
公开(公告)号：US5008739A
公开(公告)日：1991-04-16
申请号：US310419
申请日：1989-02-13
摘要： A digital processing system is described for processing luminance and chrominance signals from a single, multi-color image sensor. By concentrating signal improvements and corrections into an application-dependent post-processing phase, the pre-processing functions are isolated in a signle, generic pre-processor integrated circuit that provides fully interpolated color signals in a real-time system by utilizing a fully pipelined architecture. The pre-processor circuit separates luminance and chrominance interpolation so as to operate partly in quantized linear space and partly in quantized logarithmic space. The image signals are processed in a black reference clamp, a defect concealment circuit and a color separation and luminance interpolation circuit in linear space, using right shifts and additions to approximate predetermined multiplications. The signals are then transformed into hue signals and processed in log space for white balance and chroma (hue) interpolation. With the log green signal separately adjusted for gain, quantized red, green and blue signals are output from the pre-processor integrated circuit.
摘要翻译： 描述了用于处理来自单个多色图像传感器的亮度和色度信号的数字处理系统。 通过将信号改进和校正集中到依赖于应用的后处理阶段，预处理功能被隔离在一个通用的预处理器集成电路中，通过使用完全流水线的方式在实时系统中提供完全内插的颜色信号 建筑。 预处理器电路分离亮度和色度插值，以部分地在量化的线性空间中操作，部分地在量化对数空间中操作。 图像信号在黑色参考夹，缺陷隐藏电路和线性空间中的色分离和亮度插值电路中使用右移和相加来近似预定乘法进行处理。 然后将信号转换成色调信号，并在对数空间中进行白平衡和色度（色调）插值处理。 随着日志绿色信号单独调整增益，量化的红，绿和蓝信号从预处理器集成电路输出。
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5.发明授权Detail processing method and apparatus providing uniform processing of horizontal and vertical detail components 失效详细的处理方法和装置提供水平和垂直细节部件的统一处理
公开(公告)号：US4962419A
公开(公告)日：1990-10-09
申请号：US310456
申请日：1989-02-13
CPC分类号： H04N9/646
摘要： In a signal processing network including a color correction matrix and gamma compensation, detail processing is disclosed that includes a detail extraction circuit for generating a detail signal from an un-matrixed green signal and a detail enhancement circuit for adding the detail signal to the matrixed, gamma-corrected red, green and blue signals. The un-matrixed green signal is converted to a gamma-corrected green signal and separately input to vertical and horizontal high pass filters, which separate detail components representative of vertical and horizontal detail, respectively. The vertical detail is additionally input to a horizontal low pass filter to eliminate excessive enhancement of diagonal image components. The detail components are cored and input to the detail enhancement circuit. As a result of bypassing the color correction matrix and inserting the modified detail, including the diminished diagonal contribution, into the signal channel after gamma correction, the various detail components receive a substantially uniform visual enhancement regardless of orientation or density in the image.
摘要翻译： 在包括颜色校正矩阵和伽马补偿的信号处理网络中，公开了包括用于从非矩阵绿色信号生成细节信号的细节提取电路和用于将细节信号加到矩阵化的细节增强电路的细节处理， 伽马校正的红，绿和蓝信号。 未矩阵化的绿色信号被转换为伽马校正的绿色信号，并分别输入到垂直和水平高通滤波器，分别分别表示垂直和水平细节的细节分量。 垂直细节另外输入到水平低通滤波器以消除对角图像分量的过度增强。 细节部件是细节增强电路的核心和输入。 由于绕过颜色校正矩阵并将经修改的细节（包括减小的对角线贡献）插入到伽马校正之后的信号通道中，各种细节分量接收基本均匀的视觉增强，而与图像中的取向或密度无关。
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公开(公告)号：US5001663A
公开(公告)日：1991-03-19
申请号：US346861
申请日：1989-05-03
CPC分类号： G06F7/5443 , G06F5/01 , G06F7/523
摘要： The circuit includes a cascaded array of digital circuit blocks that together implement a matrix multiplication in each channel of a color video signal processing system. Each circuit block includes two registers for multiplying or dividing two input digital signals by respective powers of two according to programmable bit shifts. The resultant signals are arithmetically combined according to a programmable arithmetic function to provide an output signal. By mask programming the arithmetic function and the bit lenghts of the shifts for each block and by cascading the programmed blocks, the multipler coefficients of the matrix are established and the output signal represents a specified color matrix operation.
摘要翻译： 该电路包括数字电路块的级联阵列，其一起在彩色视频信号处理系统的每个通道中实现矩阵乘法。 每个电路块包括两个寄存器，用于根据可编程位移而将两个输入数字信号乘以或除以两个相应的功率。 所得信号根据可编程运算功能进行算术组合以提供输出信号。 通过对每个块的算术函数和位移的位长度进行掩码编程，并且通过级联编程的块，建立矩阵的乘法系数，并且输出信号表示指定的颜色矩阵运算。
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公开(公告)号：US07430680B2
公开(公告)日：2008-09-30
申请号：US11169006
申请日：2005-06-29
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , G06F1/12
摘要： A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal. These subsequent delay device clock signals are transmitted to the aligning device and to the sequencer before each transfer occurs.
摘要翻译： 在它们之间的数据传输之前，系统和方法使用对准装置对准两个逻辑装置的时钟信号。 在该示例中，对准装置在定序器将数据传送到存储装置之前将定序器的时钟信号与存储装置的时钟信号对准。 对准装置包括相位检测器，其接收用于控制存储装置的第一参考时钟信号和用于控制定序器的延迟信号，并产生比较时钟信号。 在用于控制与第一参考时钟信号相关的第二参考时钟信号的相位之前，对比较时钟信号进行滤波。 相位控制的第二时钟信号是对准时钟信号，其被反馈到延迟器件以产生与存储器件时钟或第一参考时钟信号对准的一个或多个后续延迟器件时钟信号。 在每次传送发生之前，这些后续的延迟装置时钟信号被发送到对准装置和定序器。
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8.发明申请Method and System for Receiving Audio, Video and Data Services with ATSC Enabled Television Sets 审中-公开用于接收具有ATSC使能电视机的音频，视频和数据业务的方法和系统公开(公告)号：US20080304596A1
公开(公告)日：2008-12-11
申请号：US11761504
申请日：2007-06-12
申请人： Loke Tan , Lionel J. D'Luna , Robindra Joshi
发明人： Loke Tan , Lionel J. D'Luna , Robindra Joshi
IPC分类号： H03D1/24
CPC分类号： H04N21/4344 , H04N21/4382
摘要： Certain aspects of a method and system for receiving audio, video and data services with advanced television systems committee (ATSC) enabled television sets may be provided. Aspects of the method may include conversion of a plurality of received quadrature amplitude modulated (QAM) signals into a plurality of vestigial side band (VSB) signals within a set-top box. The set top box may tune to each of the plurality of received QAM signals and demodulate each of the plurality of received QAM signals into a plurality of bitstreams and demultiplex the plurality of bitstreams. The demultiplexed plurality of bitstreams may be modulated into a plurality of VSB signals. The plurality of VSB signals may be modulated into a plurality of RF signals. One or more of the plurality of RF signals may be communicated to at least one of a plurality of VSB enabled television sets.
摘要翻译： 可以提供用于接收具有高级电视系统委员会（ATSC）的电视机的音频，视频和数据服务的方法和系统的某些方面。 该方法的方面可以包括将多个接收的正交幅度调制（QAM）信号转换成机顶盒内的多个残留边带（VSB）信号。 机顶盒可以调谐到多个接收到的QAM信号中的每一个，并且将多个接收的QAM信号中的每一个解调为多个比特流并对多个比特流进行解复用。 解复用的多个比特流可以被调制成多个VSB信号。 多个VSB信号可以被调制成多个RF信号。 多个RF信号中的一个或多个可以被传送到多个启用VSB的电视机中的至少一个。
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公开(公告)号：US5008563A
公开(公告)日：1991-04-16
申请号：US402585
申请日：1989-09-05
CPC分类号： H04N5/2173 , H03K3/033 , H03K5/133 , H03K2005/00195
摘要： A clock generator for producing a pulse that can be adjusted in width and position. The positive edge of an incoming clock signal is slowed by an adjustable rise time inverter with a selected bias voltage until a selected threshold voltage level is met by a Schmitt trigger. The output from the Schmitt trigger is directed through a similar delay circuit to establish the pulse width of the pulse.
摘要翻译： 用于产生可以在宽度和位置上调节的脉冲的时钟发生器。 输入时钟信号的上升沿由具有选定偏置电压的可调节上升时间反相器减慢，直到施密特触发器满足选定的阈值电压电平。 来自施密特触发器的输出通过类似的延迟电路被引导以建立脉冲的脉冲宽度。
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公开(公告)号：US07515504B2
公开(公告)日：2009-04-07
申请号：US11969404
申请日：2008-01-04
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G06F13/4243 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , H03K2005/00052 , H03L7/0805 , H03L7/0812 , H03L7/183 , H03L7/23
摘要： A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
摘要翻译： 一种系统和方法用于允许电路和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。
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