公开(公告)号：US07023253B2

公开(公告)日：2006-04-04

申请号：US10882159

申请日：2004-07-02

Applicant: Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

Inventor： Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

IPC: H03K5/00

CPC classification number: H03F3/217 ,  H02M3/1588 ,  H03K7/08 ,  Y02B70/1466

Abstract: In a noise sensitivity improved switching system and method thereof, comprised sensing the output voltage of the switching system to generate a feedback signal, respectively amplifying the feedback signal by two gains to generate two signals in phase or out of phase, filtering one of the two amplified signals, and summing or comparing the filtered signal and the other one, thereby reducing the noise interference to the switching system.

Abstract translation: 在噪声敏感度改进的开关系统及其方法中，包括感测开关系统的输出电压以产生反馈信号，分别通过两个增益来放大反馈信号以产生相或异相的两个信号，滤波两个 放大信号，并对滤波后的信号进行求和或比较，从而降低对交换系统的噪声干扰。

公开(公告)号：US06946823B2

公开(公告)日：2005-09-20

申请号：US10846601

申请日：2004-05-17

Applicant: Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

Inventor： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

IPC: H02M3/158 ,  G05F1/575

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A delta-sigma DC-to-DC converter comprises a pair of high-side and low-side switches switched to convert an input voltage to an output voltage, a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a differential current, a charging circuit connected with the differential current to generate a charging voltage, and a driver to compare the charging voltage with two reference signals to generate the pair of low-side and high-side driving signals.

Abstract translation: Δ-ΣDC-DC转换器包括一对开关将输入电压转换为输出电压的高侧和低侧开关，感测电路以感测转换器的输出电压以产生反馈信号， 用于放大反馈信号和阈值信号之间的差异以产生差分电流的跨导放大器，与差分电流连接以产生充电电压的充电电路，以及将充电电压与两个参考信号进行比较的驱动器，以产生 一对低侧和高侧驱动信号。

公开(公告)号：US07233134B2

公开(公告)日：2007-06-19

申请号：US10846569

申请日：2004-05-17

Applicant: Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

Inventor： Kent Huang ,  Liang-Pin Tai ,  Hung-I Wang ,  Jian-Rong Huang ,  Kuo-Ping Liu ,  Yu-Fan Liao

IPC: G05F1/40

CPC classification number: H02M3/158

Abstract: A DC-to-DC converter comprises a sense circuit to sense the output voltage of the converter to generate a feedback signal, a transconductive amplifier to amplify a difference between the feedback signal and a threshold signal to generate a first current and to generate a second current in response to a load transient, a charging circuit connected with the first current to generate a charging voltage, a driver to compare the charging voltage with two reference signals to generate a pair of low-side and high-side driving signals, and a fast response circuit to compare a load transient signal corresponding to the second current with a third reference signal to generate a bypass signal to drive the output stage of the converter in the load transient.

Abstract translation: DC-DC转换器包括用于感测转换器的输出电压以产生反馈信号的感测电路，用于放大反馈信号和阈值信号之间的差异的跨导放大器以产生第一电流并产生第二电流 响应于负载瞬变的电流，与第一电流连接以产生充电电压的充电电路，将充电电压与两个参考信号进行比较的驱动器，以产生一对低侧和高侧驱动信号，以及 快速响应电路，将与第二电流相对应的负载瞬态信号与第三参考信号进行比较，以产生旁路信号，以在负载瞬变中驱动转换器的输出级。

公开(公告)号：US07230406B2

公开(公告)日：2007-06-12

申请号：US11210812

申请日：2005-08-25

Applicant: Kent Huang ,  Liang-Pin Tai

Inventor： Kent Huang ,  Liang-Pin Tai

IPC: G05F1/00

CPC classification number: H02M3/158 ,  H02M3/1584

Abstract: A fixed-frequency current mode converter comprises a power stage to produce an inductor current and an output voltage, an error amplifier to generate an error signal from the difference between the output voltage and a reference voltage varied with the inductor current, a comparator to compare the error signal with a ramp signal varied with the inductor current to generate a comparison signal, and a PWM generator to generate a PWM signal in response to a fixed-frequency clock and the comparison signal to drive the power stage. A second comparator is further comprised to compare the error signal with a second reference voltage varied with the inductor current, and generates a second comparison signal to reset the clock when the error signal is lower than the second reference voltage.

Abstract translation: 固定频率电流模式转换器包括产生电感电流和输出电压的功率级，误差放大器，根据输出电压和与电感电流变化的参考电压之间的差异产生误差信号，比较器进行比较 具有斜坡信号的误差信号随着电感器电流而变化以产生比较信号，以及PWM发生器，以响应于固定频率时钟和比较信号产生PWM信号以驱动功率级。 还包括第二比较器，用于将误差信号与随电感器电流变化的第二参考电压进行比较，并且当误差信号低于第二参考电压时产生第二比较信号以复位时钟。

公开(公告)号：US20060043943A1

公开(公告)日：2006-03-02

申请号：US11210812

申请日：2005-08-25

Applicant: Kent Huang ,  Liang-Pin Tai

Inventor： Kent Huang ,  Liang-Pin Tai

IPC: G05F1/656

CPC classification number: H02M3/158 ,  H02M3/1584

Abstract: A fixed-frequency current mode converter comprises a power stage to produce an inductor current and an output voltage, an error amplifier to generate an error signal from the difference between the output voltage and a reference voltage varied with the inductor current, a comparator to compare the error signal with a ramp signal varied with the inductor current to generate a comparison signal, and a PWM generator to generate a PWM signal in response to a fixed-frequency clock and the comparison signal to drive the power stage. A second comparator is further comprised to compare the error signal with a second reference voltage varied with the inductor current, and generates a second comparison signal to reset the clock when the error signal is lower than the second reference voltage.

Abstract translation: 固定频率电流模式转换器包括产生电感电流和输出电压的功率级，误差放大器，根据输出电压和与电感电流变化的参考电压之间的差异产生误差信号，比较器进行比较 具有斜坡信号的误差信号随着电感器电流而变化以产生比较信号，以及PWM发生器，以响应于固定频率时钟和比较信号产生PWM信号以驱动功率级。 还包括第二比较器，用于将误差信号与随电感器电流变化的第二参考电压进行比较，并且当误差信号低于第二参考电压时产生第二比较信号以复位时钟。

公开(公告)号：US20050017767A1

公开(公告)日：2005-01-27

申请号：US10882159

申请日：2004-07-02

Applicant: Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

Inventor： Jian-Rong Huang ,  Kuo-Ping Liu ,  Kent Huang ,  Liang-Pin Tai

IPC: H02M3/158 ,  H03F3/217 ,  H03K7/08 ,  H03B1/00

CPC classification number: H03F3/217 ,  H02M3/1588 ,  H03K7/08 ,  Y02B70/1466

Abstract: In a noise sensitivity improved switching system and method thereof, comprised sensing the output voltage of the switching system to generate a feedback signal, respectively amplifying the feedback signal by two gains to generate two signals in phase or out of phase, filtering one of the two amplified signals, and summing or comparing the filtered signal and the other one, thereby reducing the noise interference to the switching system.

Abstract translation: 在噪声敏感度改进的开关系统及其方法中，包括感测开关系统的输出电压以产生反馈信号，分别通过两个增益来放大反馈信号以产生相或异相的两个信号，滤波两个 放大信号，并对滤波后的信号进行求和或比较，从而降低对交换系统的噪声干扰。

公开(公告)号：US07786604B2

公开(公告)日：2010-08-31

申请号：US11797779

申请日：2007-05-08

Applicant: Liang-Pin Tai

Inventor： Liang-Pin Tai

IPC: H01L23/34

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device package comprises a first semiconductor die having a first source region, a first gate region, and a first drain region attached on a first leadframe, a second semiconductor die having a second source region, a second gate region, and a second drain region attached on a second leadframe, and several pins electrically connected to the leadframes and source and gate regions. The second leadframe is electrically connected to the first source region. The pins connected to the first leadframe and second source region are on a side of the package, and the pins connected to the first gate region, second leadframe, and second gate region are on another side of the package.

Abstract translation: 半导体器件封装包括第一半导体管芯，其具有第一源区域，第一栅极区域和附接在第一引线框架上的第一漏极区域，具有第二源极区域，第二栅极区域和第二漏极区域的第二半导体管芯 区域，以及连接到引线框架和源极和栅极区域的几个引脚。 第二引线框电连接到第一源区。 连接到第一引线框架和第二源极区域的引脚位于封装的一侧，并且连接到第一栅极区域，第二引线框架和第二栅极区域的引脚在封装的另一侧上。

公开(公告)号：US07701190B2

公开(公告)日：2010-04-20

申请号：US11657003

申请日：2007-01-24

Applicant: Jiun-Chiang Chen ,  Liang-Pin Tai

Inventor： Jiun-Chiang Chen ,  Liang-Pin Tai

IPC: G05F1/00

CPC classification number: H02M3/1584

Abstract: For a DC-to-DC converter including a plurality of channels for converting an input voltage to an output voltage, a control circuit comprises a load transient detector to detect the output voltage to provide a quick response signal. In a load transient, the quick response signal triggers a quick transient response period to increase the operational frequency of the converter.

Abstract translation: 对于包括用于将输入电压转换为输出电压的多个通道的DC-DC转换器，控制电路包括检测输出电压以提供快速响应信号的负载瞬变检测器。 在负载瞬变中，快速响应信号触发快速的瞬态响应周期以增加转换器的工作频率。

公开(公告)号：US20090237062A1

公开(公告)日：2009-09-24

申请号：US12385721

申请日：2009-04-17

Applicant: Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

Inventor： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC: G05F3/24

CPC classification number: H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

公开(公告)号：US20090206922A1

公开(公告)日：2009-08-20

申请号：US12385718

申请日：2009-04-17

Applicant: Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

Inventor： Liang-Pin Tai ,  Jing-Meng Liu ,  Hung-Der Su

IPC: G05F3/02

CPC classification number: H01L27/098 ,  H01L27/0744 ,  H01L29/7722 ,  H01L29/8083

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.