公开(公告)号：US08930866B2

公开(公告)日：2015-01-06

申请号：US13794024

申请日：2013-03-11

申请人： Hung-Cheng Sung ,  Yue-Der Chih ,  Chia-Hsing Chen

发明人： Hung-Cheng Sung ,  Yue-Der Chih ,  Chia-Hsing Chen

IPC分类号： G06F17/50 ,  H01L29/66

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/78 ,  H01L27/0207 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

摘要翻译： 一种设计电荷俘获存储器阵列的方法，包括设计浮栅存储器阵列布局。 浮动栅极存储器布局包括第一类型的晶体管，浮动栅极存储器阵列布局的存储器单元之间的电连接，第一输入/输出（I / O）接口，第一类型的电荷泵和I / O块 。 该方法还包括使用处理器来修改浮动栅极存储器阵列布局，以用与第一类型的晶体管不同的第二类型的晶体管代替第一类型的晶体管。 该方法还包括确定I / O块和第二类型的晶体管之间的工作电压差。 该方法还包括使用处理器修改浮动栅极存储器阵列布局，以基于所确定的工作电压差来修改第一电荷泵。

公开(公告)号：US08610220B2

公开(公告)日：2013-12-17

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20140094009A1

公开(公告)日：2014-04-03

申请号：US14106100

申请日：2013-12-13

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20130307080A1

公开(公告)日：2013-11-21

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/088 ,  H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US09390799B2

公开(公告)日：2016-07-12

申请号：US13460487

申请日：2012-04-30

申请人： Yue-Der Chih

发明人： Yue-Der Chih

IPC分类号： G11C16/04 ,  G11C11/56 ,  H01L29/70 ,  H01L29/40 ,  H01L29/423 ,  H01L29/792

CPC分类号： G11C16/0458 ,  G11C11/5621 ,  H01L29/42348 ,  H01L29/7923

摘要： Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data.

摘要翻译： 非易失性存储单元和方法。 在一种装置中，形成在半导体衬底的一部分中的非易失性存储单元的阵列包括具有第一位单元和第二位单元的第一存储单元; 具有第三位单元和第四位单元的第二存储单元; 以及耦合到多条列线的列多路复用器，所述列线中选定的列线耦合到所述第一和第二存储单元的第一源极/漏极端子并且耦合到所述第一和第二存储单元的第二源极/漏极端子 列多路复用器将电压耦合到与数据相对应的连接到第一存储单元的列线之一，并且将电压耦合到与互补数据对应的连接到第二存储单元的列线之一。

公开(公告)号：US09058872B2

公开(公告)日：2015-06-16

申请号：US13755445

申请日：2013-01-31

申请人： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

发明人： Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C11/412 ,  G11C14/00

CPC分类号： G11C13/0004 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/412 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/009 ,  G11C2213/79

摘要： A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node.

摘要翻译： 基于电阻的随机存取存储器电路包括第一数据线，第二数据线，多个存储单元，第一驱动单元和第二驱动单元。 存储单元与第一和第二数据线并行布置。 每个存储器单元耦合在第一数据线和第二数据线之间。 第一驱动单元与第一和第二数据线的第一端耦合。 第一驱动单元被配置为将第一数据线和第二数据线中的一个电耦合到第一电压节点。 第二驱动单元与第一和第二数据线的第二端耦合。 第二驱动单元被配置为将第一数据线和第二数据线中的另一个电耦合到第二电压节点。

公开(公告)号：US08593854B1

公开(公告)日：2013-11-26

申请号：US13476366

申请日：2012-05-21

申请人： Yue-Der Chih ,  Luan Conn Tran

发明人： Yue-Der Chih ,  Luan Conn Tran

IPC分类号： G11C11/00

CPC分类号： H01L45/04 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

摘要： An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array.

摘要翻译： 用于电阻RAM（RRAM）器件的阵列和形成方法提供了同时选择多个位单元并且在所选位单元内同时形成RRAM电阻元件。 每个位单元都包括电阻元件和晶体管，并且沿着垂直位线垂直布置。 位单元的电阻元件耦合到与字线平行并垂直于垂直位线的源极线。 位线保持不同的偏置。 高电压施加到耦合到沿着多于一个垂直位线布置的位单元的相邻电阻元件的源极线之一。 当相关联的晶体管导通足够高的栅极电压时，沿着位线之一的期望的RRAM电阻元件形成，而不会压迫阵列的其它位单元。

公开(公告)号：US08509003B2

公开(公告)日：2013-08-13

申请号：US13237282

申请日：2011-09-20

申请人： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

发明人： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C16/06 ,  G11C11/56

CPC分类号： G11C11/5642 ,  G11C11/1673 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5685 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

摘要： A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.

摘要翻译： 用于读取随机存取存储器（RAM）单元的读取架构包括多电平读出放大器，多电平读出放大器包括多个读出放大器，每个读出放大器具有相应的感测阈值和相应的感测输出，以及存储器 模块耦合到多电平读出放大器，用于存储多电平读出放大器的感测输出。 存储模块存储对应于RAM单元的第一读取的第一组感测输出，并且存储对应于RAM单元的第二读取的第二组感测输出。 该架构还包括用于比较第一和第二组感测输出的判定模块，并且基于该比较确定RAM单元的数据状态。

公开(公告)号：US20130070519A1

公开(公告)日：2013-03-21

申请号：US13237282

申请日：2011-09-20

申请人： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

发明人： Kai-Chun Lin ,  Hung-Chang Yu ,  Yue-Der Chih

IPC分类号： G11C11/16

CPC分类号： G11C11/5642 ,  G11C11/1673 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5685 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

摘要： A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.

摘要翻译： 用于读取随机存取存储器（RAM）单元的读取架构包括多电平读出放大器，多电平读出放大器包括多个读出放大器，每个读出放大器具有相应的感测阈值和相应的感测输出，以及存储器 模块耦合到多电平读出放大器，用于存储多电平读出放大器的感测输出。 存储模块存储对应于RAM单元的第一读取的第一组感测输出，并且存储对应于RAM单元的第二读取的第二组感测输出。 该架构还包括用于比较第一和第二组感测输出的判定模块，并且基于该比较确定RAM单元的数据状态。

公开(公告)号：US20120106259A1

公开(公告)日：2012-05-03

申请号：US12915310

申请日：2010-10-29

申请人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

发明人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10

摘要： A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation.

摘要翻译： 一种方法包括在相同的编程周期中对多个存储单元执行第一编程操作; 以及对所述多个存储单元执行验证操作以在所述多个存储器单元中找到故障存储器单元，其中在所述第一编程操作中所述故障存储单元未成功编程; 以及对所述故障存储器单元执行第二编程操作。 在第二个编程操作中，没有编程在第一个编程操作中成功编程的通过的存储单元。