公开(公告)号：US20060106972A1

公开(公告)日：2006-05-18

申请号：US10990189

申请日：2004-11-15

申请人： Sergey Gorobets ,  Alan Bennett ,  Peter Smith ,  Alan Sinclair ,  Kevin Conley ,  Philip Royall

发明人： Sergey Gorobets ,  Alan Bennett ,  Peter Smith ,  Alan Sinclair ,  Kevin Conley ,  Philip Royall

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated in a manner to level out the wear of the individual blocks through repetitive erasing and re-programming. This may be accomplished without use of counts of the number of times the individual blocks experience erase and re-programming but such counts can optionally aid in carrying out the wear leveling process. Individual active physical blocks are chosen to be exchanged with those of an erased block pool in a predefined order.

摘要翻译： 将其存储单元分组为同时可擦除的单元块的诸如闪存EEPROM系统的可重新编程的非易失性存储器系统以通过重复擦除和重新排列来平衡各个块的磨损的方式操作， 编程。 这可以在不使用单个块经历擦除和重新编程的次数的计数的情况下实现，但是这样的计数可以可选地有助于执行磨损均衡过程。 选择单独的活动物理块以按预定义的顺序与擦除的块池的块进行交换。

公开(公告)号：US20060020745A1

公开(公告)日：2006-01-26

申请号：US11022369

申请日：2004-12-23

申请人： Kevin Conley ,  Alan Sinclair ,  Peter Smith

发明人： Kevin Conley ,  Alan Sinclair ,  Peter Smith

IPC分类号： G06F12/00

CPC分类号： G06F3/064 ,  G06F3/061 ,  G06F3/0643 ,  G06F3/0679 ,  G06F12/0246

摘要： Techniques for managing data in a non-volatile memory system (e.g., Flash Memory) are disclosed. A controller can use information relating to a host's file system, which is stored by the host on non-volatile memory, to determine if one or more clusters (or sectors with clusters) are currently allocated. The controller can use the information relating to the host's file system to identify when the host is sending data to the next free cluster and to store such data in a sequential format by copying data from other locations in the non-volatile memory.

摘要翻译： 公开了用于在非易失性存储器系统（例如，闪存）中管理数据的技术。 控制器可以使用由主机在非易失性存储器上存储的主机文件系统相关的信息来确定当前是否分配了一个或多个集群（或具有集群的扇区）。 控制器可以使用与主机文件系统相关的信息来识别主机何时向下一个空闲簇发送数据，并通过从非易失性存储器中的其他位置复制数据来以顺序格式存储这些数据。

公开(公告)号：US20050251617A1

公开(公告)日：2005-11-10

申请号：US10841379

申请日：2004-05-07

申请人： Alan Sinclair ,  Sergey Gorobets ,  Kevin Conley ,  Carlos Gonzalez

发明人： Alan Sinclair ,  Sergey Gorobets ,  Kevin Conley ,  Carlos Gonzalez

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0893 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C14/0036 ,  G11C14/0045

摘要： The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host.

摘要翻译： 本发明提出了一种混合非易失性系统，其使用基于两个或多个不同的非易失性存储器技术的非易失性存储器，以利用这些技术相对于其他技术的相对优点。 在示例性实施例中，存储器系统包括控制器和闪存，其中控制器具有基于诸如FeRAM的替代技术的非易失性RAM。 闪存用于存储用户数据，并且控制器中的非易失性RAM用于由控制器用于管理闪存中的主机数据的存储的系统控制数据。 在控制器中使用替代的非易失性存储器技术允许更快速地访问最近的控制数据的非易失性拷贝，因为它可以逐点更新。 在另一个示例性实施例中，备用非易失性存储器用作高速缓存，其中数据可以在其被写入存储器或读回主机之前安全地分级。

公开(公告)号：US20060136687A1

公开(公告)日：2006-06-22

申请号：US11022462

申请日：2004-12-21

申请人： Kevin Conley ,  Peter Smith

发明人： Kevin Conley ,  Peter Smith

IPC分类号： G06F12/16

CPC分类号： G11C16/10 ,  G11C16/26

摘要： The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.

摘要翻译： 片上复制处理被扩展，使得可以在可以在不同芯片上的两个块之间，同一芯片上的不同平面或同一芯片的同一平面上复制数据。 更具体地说，这里描述的方法提供了允许在存储器系统中的任何两个位置之间复制数据的单个数据复制机制。 示例性实施例使用EDO型定时。 根据另一方面，可以在控制器中即时更新重新定位的数据的所选部分，例如传送页面中的所选择的单词。 除了将数据集直接从源阵列的读缓冲器传送到目的地阵列的写缓冲器之外，如果需要，数据组可以同时复制到控制器中，其中可以执行错误检测和校正操作 它。

公开(公告)号：US20070211532A1

公开(公告)日：2007-09-13

申请号：US11748077

申请日：2007-05-14

申请人： Carlos Gonzalez ,  Kevin Conley

发明人： Carlos Gonzalez ,  Kevin Conley

IPC分类号： G11C11/34

CPC分类号： G06F11/106 ,  G06F11/1068 ,  G11C8/08

摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

摘要翻译： 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回。 当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。

公开(公告)号：US20070143545A1

公开(公告)日：2007-06-21

申请号：US11671394

申请日：2007-02-05

申请人： Kevin Conley ,  Reuven Elhamias

发明人： Kevin Conley ,  Reuven Elhamias

IPC分类号： G06F12/00 ,  G06F13/28

CPC分类号： G06F12/0862 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/2146 ,  G06F2212/282 ,  G06F2212/502

摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

摘要翻译： 介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以不同策略操作的段。 缓存策略包括直写，写入和预读。 直写和回写策略可能会提高速度。 预读高速缓存允许在缓冲器高速缓存和非易失性存储器之间更有效地使用总线。 会话命令允许通过保证防止功率损耗来将数据保存在易失性存储器中。

公开(公告)号：US20070143533A1

公开(公告)日：2007-06-21

申请号：US11314933

申请日：2005-12-21

申请人： Kevin Conley

发明人： Kevin Conley

IPC分类号： G06F12/00 ,  G06F13/28

CPC分类号： G06F21/32

摘要： Method for a portable memory storage device is provided. The method includes, enrolling the device after the device interfaces with a host system and an application is launched that requests a user to provide voice input; receiving the user voice input and storing the voice input as a template for subsequent user access; wherein the template is stored in non-volatile memory cells of the device; and authenticating a user by receiving user voice input and comparing the voice input with the stored template, wherein access to user files is provided after the user is authenticated.

摘要翻译： 提供了一种用于便携式存储器存储装置的方法。 该方法包括：在设备与主机系统接口并启动请求用户提供语音输入的应用之后注册设备; 接收用户语音输入并存储语音输入作为后续用户访问的模板; 其中所述模板存储在所述设备的非易失性存储单元中; 以及通过接收用户语音输入并将语音输入与存储的模板进行比较来认证用户，其中在用户被认证之后提供对用户文件的访问。

公开(公告)号：US20070103977A1

公开(公告)日：2007-05-10

申请号：US11270198

申请日：2005-11-08

申请人： Kevin Conley ,  Yoran Cedar

发明人： Kevin Conley ,  Yoran Cedar

IPC分类号： G11C16/06

CPC分类号： G11C29/81 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/808 ,  G11C29/82

摘要： In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

摘要翻译： 在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。 一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。 重新映射作为初始测试和配置的一部分完成。 具体硬件可用于方案或固件在内存控制器中可实现的方案。

公开(公告)号：US20050257120A1

公开(公告)日：2005-11-17

申请号：US10846289

申请日：2004-05-13

申请人： Sergey Gorobets ,  Kevin Conley

发明人： Sergey Gorobets ,  Kevin Conley

IPC分类号： G06F3/00 ,  G11C7/10 ,  G11C16/34 ,  G11C29/00

CPC分类号： G06F12/0246 ,  G06F11/1008 ,  G11C7/1039 ,  G11C7/1051 ,  G11C16/3436

摘要： The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

摘要翻译： 本发明提出了用于具有写入操作的读取操作的流水线的方法和架构。 特别地，提出了用于流水线数据迁移操作的方法，其允许在控制器被重写之前检查和校正控制器中的数据，但是减少或消除通常会产生的额外时间损失。 描述了许多架构改进以便于这些方法，包括：在存储器上引入两个寄存器，每个寄存器可由控制器独立访问; 允许在写入第二个寄存器时写入第一个存储器寄存器; 在存储器中引入两个寄存器，其中寄存器的内容可以交换。

公开(公告)号：US20050146939A1

公开(公告)日：2005-07-07

申请号：US11058359

申请日：2005-02-14

申请人： Kevin Conley ,  Yoram Cedar

发明人： Kevin Conley ,  Yoram Cedar

IPC分类号： G06F5/06 ,  G06F12/00 ,  G11C7/10 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10

CPC分类号： G11C16/105 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/22

摘要： The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

摘要翻译： 本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。 数据从控制器传送到第一存储器芯片，并且开始编程操作。 当该第一存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二存储器芯片，并且使该编程操作在该芯片中开始。 一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。 以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。 呈现了两组实施例，一种将缓冲器中的主机数据保留，直到该数据的成功编程被确认为止，并且不需要实现该成功，并且不保留数据从而实现更高的数据编程吞吐量 。