公开(公告)号：US6046097A

公开(公告)日：2000-04-04

申请号：US274599

申请日：1999-03-23

申请人： Kevin Hsieh ,  Kun-Chih Wang ,  Wen-Yi Hsieh

发明人： Kevin Hsieh ,  Kun-Chih Wang ,  Wen-Yi Hsieh

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76843

摘要： A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto the substrate, wherein the direction of the first deposition is about vertical to the surface of the substrate, and therefore the bottom of the contact holes is then substantially deposited with the conductive material. Next, the chuck is secondly adjusted so that it has a tilt angle between the direction of the second deposition and rotation axis of the chuck. Finally, the chuck is continuously rotated and the conductive material is secondly deposited onto the substrate, and therefore the sidewall of the contact holes is then substantially deposited with the conductive material.

摘要翻译： 公开了一种用于改善接触孔的台阶覆盖的沉积方法。 该方法包括最初将半导体衬底放置在室的卡盘上，其中衬底具有一些接触孔。 首先调整卡盘，并且首先将导电材料沉积到基底上，其中第一沉积的方向大约垂直于基底的表面，因此接触孔的底部然后基本上沉积有导电材料。 接下来，卡盘被二次调节，使得其在第二沉积的方向和卡盘的旋转轴线之间具有倾斜角。 最后，卡盘连续旋转，导电材料第二次沉积在基片上，因此接触孔的侧壁然后基本上沉积有导电材料。

公开(公告)号：US06180484B2

公开(公告)日：2001-01-30

申请号：US09140776

申请日：1998-08-26

申请人： Kun-Chih Wang ,  Wen-Yi Hsieh

发明人： Kun-Chih Wang ,  Wen-Yi Hsieh

IPC分类号： H01L2120

CPC分类号： H01L28/60 ,  C23C16/14 ,  C23C16/56 ,  H01L21/7684 ,  H01L21/76877

摘要： The present invention proposes a method for forming a tungsten film with a good surface property and utilizes a chemical plasma treatment to round the tungsten surface and to improve the leakage issue of tungsten conductive film. A fabrication of a DRAM cell capacitor with tungsten bottom electrode is described for a preferred embodiment. Forming an inter-layer dielectric on a semiconductor substrate, a tungsten layer is formed thereon. A chemical plasma treatment is carried out to round the tungsten surface spires and result in a better surface properties. The tungsten layer is patterned to serve as the bottom electrode, and another dielectric layer is formed to cover the bottom electrode of tungsten. Finally, the top storage electrode is formed to finish the present process.

摘要翻译： 本发明提出了一种形成具有良好表面性能的钨膜的方法，并利用化学等离子体处理使钨表面圆弧化并改善了钨导电膜的泄漏问题。 对于优选实施例描述了具有钨底电极的DRAM单元电容器的制造。 在半导体衬底上形成层间电介质，在其上形成钨层。 进行化学等离子体处理以使钨表面尖锐化，并产生更好的表面性能。 图案化钨层用作底部电极，并且形成另一个电介质层以覆盖钨的底部电极。 最后，形成顶部存储电极以完成本工艺。

公开(公告)号：US06169028A

公开(公告)日：2001-01-02

申请号：US09237787

申请日：1999-01-26

申请人： Kun-Chih Wang ,  Ming-Sheng Yang ,  Wen-Yi Hsieh

发明人： Kun-Chih Wang ,  Ming-Sheng Yang ,  Wen-Yi Hsieh

IPC分类号： H10L2144

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76807

摘要： A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.

摘要翻译： 一种制造金属互连结构的方法。 提供了包括其中的导电层的半导体衬底。 在半导体衬底上形成电介质层。 去除介电层的一部分以在其中形成双镶嵌开口和沟槽，其中双镶嵌开口暴露导电层。 沟槽大于双镶嵌开口。 在电介质层上形成保形阻挡层。 在阻挡层上形成保形金属层以填充双镶嵌开口并部分填充沟槽。 定位在沟槽中的金属层的厚度等于沟槽的深度。 在金属层上形成共形盖层。 执行CMP处理以去除沟槽外部的覆盖层，金属层和阻挡层，并且在双镶嵌开口外部。

公开(公告)号：US6080660A

公开(公告)日：2000-06-27

申请号：US32682

申请日：1998-02-27

申请人： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

发明人： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76805

摘要： A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

摘要翻译： 一种用于制造通孔结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上形成导电线和电介质层。 接下来，进行光刻和第一蚀刻操作，从而形成暴露导电线表面的电介质层中的开口。 第一蚀刻操作使用多种蚀刻剂，包括具有最高浓度的氟代丁烷。 由于在开口的底部存在再入口结构，因此进行第二蚀刻操作。 在第二蚀刻操作中，导电线的一部分被蚀刻固定的时间间隔以控制蚀刻程度。 因此，在开口的底部形成倾斜表面，并且消除了再入口结构。 在平坦化的底部，随后沉积材料的阶梯覆盖率增加。

公开(公告)号：US06245380B1

公开(公告)日：2001-06-12

申请号：US09249582

申请日：1999-02-11

申请人： Shih-Wei Sun ,  Wen-Yi Hsieh ,  Water Lur ,  Kun-Chih Wang

发明人： Shih-Wei Sun ,  Wen-Yi Hsieh ,  Water Lur ,  Kun-Chih Wang

IPC分类号： B05D512

CPC分类号： H01L24/05 ,  H01L21/76807 ,  H01L21/76847 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014

摘要： A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.

摘要翻译： 通过在所提供的金属间介电层上形成保形阻挡层，开始形成焊盘的方法。 在阻挡层上形成第一金属层以部分地填充沟槽。 在第一金属层上形成薄胶层。 在胶层上形成第二金属层以填充沟槽。 部分去除第二金属层，胶层，第一金属层和阻挡层，以露出介质层。 因此在沟槽中形成接合焊盘结构。 焊盘结构包括第一金属焊盘和第二金属焊盘。

公开(公告)号：US06339025B1

公开(公告)日：2002-01-15

申请号：US09304436

申请日：1999-04-03

申请人： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

发明人： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

IPC分类号： H01L2144

CPC分类号： H01L21/76886 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867

摘要： A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

摘要翻译： 一种制造铜覆盖层的方法。 在暴露的铜层上形成富氮的氮化物层。 由于富含硅的氮化物层内部具有更多的悬空键，富硅氮化物层中的硅容易与铜反应，并且在铜和富硅氮化物层之间形成铜硅化物层。 因此，可以提高铜和富硅氮化物层的粘合性。

公开(公告)号：US6048796A

公开(公告)日：2000-04-11

申请号：US211891

申请日：1998-12-15

申请人： Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang ,  Chih-Chien Liu ,  Water Lur

发明人： Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang ,  Chih-Chien Liu ,  Water Lur

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/7684 ,  H01L21/76829

摘要： A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

摘要翻译： 描述了一种用于制造多层金属互连的方法。 该方法包括以下步骤：提供衬底，然后在衬底上形成线。 在基板和导线上形成电介质层，在电介质层上形成保护层。 通过图案化保护层和电介质层形成开口，并且在保护层和开口中形成阻挡层。 在阻挡层上形成铜层并填充开口。 通过化学机械抛光去除铜层和阻挡层的一部分。

公开(公告)号：US06287967B1

公开(公告)日：2001-09-11

申请号：US09451585

申请日：1999-11-30

申请人： Kevin Hsieh ,  Michael W C Huang ,  Wen-Yi Hsieh

发明人： Kevin Hsieh ,  Michael W C Huang ,  Wen-Yi Hsieh

IPC分类号： H01L2976

CPC分类号： H01L29/66515 ,  H01L29/41783 ,  H01L29/665

摘要： A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C49 phase into a low-resistance C54 phase.

摘要翻译： 自对准硅化物工艺。 衬底至少形成有晶体管。 在衬底上形成薄金属层。 执行第一快速热处理以使金属层与栅极和源极/漏极区的多晶硅反应以形成第一金属硅化物层。 去除不与多晶硅反应的金属层。 执行选择性升高的自对准硅化物工艺以在第一金属硅化物层上形成第二金属硅化物层。 执行第二快速热处理以将第一金属硅化物层和第二金属硅化物层从高电阻C49相转变成低电阻C54相。

公开(公告)号：US08434949B2

公开(公告)日：2013-05-07

申请号：US12892952

申请日：2010-09-29

申请人： Chun-Hsiung Wang ,  Wen-Yi Hsieh ,  Yen-Chih Chang ,  Ming-Lun Szu ,  Chien-Hung Lee

发明人： Chun-Hsiung Wang ,  Wen-Yi Hsieh ,  Yen-Chih Chang ,  Ming-Lun Szu ,  Chien-Hung Lee

IPC分类号： G02B6/38

CPC分类号： G02B6/32 ,  G02B6/3853 ,  G02B6/3865 ,  G02B6/3882 ,  G02B6/3885

摘要： An optical fiber connector includes a pair of optical fibers and a seat defining a pair of lenses at a front edge thereof and passageways aligned with the lenses respectively and receiving the optical fibers. The seat defines a pair of first apertures at a first surface thereof communicating with the passageways, and a pair of second aperture at a second surface thereof opposite to the first surface communicating with the passageways. Rear insides of the first apertures are aligned with front insides of the second apertures.

摘要翻译： 光纤连接器包括一对光纤和在其前边缘处限定一对透镜的座，并且分别与透镜对准并接收光纤。 座位在其与通道连通的第一表面处限定一对第一孔，以及在与通道连通的与第一表面相对的第二表面处的一对第二孔。 第一孔的后内侧与第二孔的前内侧对准。

公开(公告)号：US08342870B2

公开(公告)日：2013-01-01

申请号：US13045546

申请日：2011-03-11

申请人： Wen-Yi Hsieh ,  Ke-Hao Chen

发明人： Wen-Yi Hsieh ,  Ke-Hao Chen

IPC分类号： H01R13/62

CPC分类号： G01R1/0458

摘要： A socket connector (100) comprises a socket body (5), a plurality of contacts (3) received in the socket body (5), a lid (1) movably mounted on the socket body (5) and moving up and down along a vertical direction, a moving plate (4) movably mounted upon the socket body (5) and moving along a horizontal direction and an operating lever (2) located between the lid (1) and the moving plate (4), the operating lever (2) comprises a press member (22), the press member (22) presses on the top surface of the moving plate (4) to prevent the floating of the moving plate (4) in the vertical direction.

摘要翻译： 插座连接器（100）包括插座主体（5），容纳在插座主体（5）中的多个触点（3），可移动地安装在插座主体（5）上并沿着 垂直方向，可移动地安装在插座主体（5）上并沿着水平方向移动的移动板（4）和位于盖（1）和移动板（4）之间的操作杆（2） （2）包括按压构件（22），所述按压构件（22）压在所述移动板（4）的顶表面上，以防止所述移动板（4）在垂直方向上浮动。