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40 条记录 (耗时 0.021 秒)

    Deposition method with improved step coverage
    1.
    发明授权
    Deposition method with improved step coverage 有权
    沉积方法具有改进的台阶覆盖

    公开(公告)号：US6046097A

    公开(公告)日：2000-04-04

    申请号：US274599

    申请日：1999-03-23

    申请人： Kevin Hsieh ,  Kun-Chih Wang ,  Wen-Yi Hsieh

    发明人： Kevin Hsieh ,  Kun-Chih Wang ,  Wen-Yi Hsieh

    IPC分类号： H01L21/768 ,  H01L21/28

    CPC分类号： H01L21/76843

    摘要： A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto the substrate, wherein the direction of the first deposition is about vertical to the surface of the substrate, and therefore the bottom of the contact holes is then substantially deposited with the conductive material. Next, the chuck is secondly adjusted so that it has a tilt angle between the direction of the second deposition and rotation axis of the chuck. Finally, the chuck is continuously rotated and the conductive material is secondly deposited onto the substrate, and therefore the sidewall of the contact holes is then substantially deposited with the conductive material.

    摘要翻译： 公开了一种用于改善接触孔的台阶覆盖的沉积方法。 该方法包括最初将半导体衬底放置在室的卡盘上，其中衬底具有一些接触孔。 首先调整卡盘，并且首先将导电材料沉积到基底上，其中第一沉积的方向大约垂直于基底的表面，因此接触孔的底部然后基本上沉积有导电材料。 接下来，卡盘被二次调节，使得其在第二沉积的方向和卡盘的旋转轴线之间具有倾斜角。 最后，卡盘连续旋转，导电材料第二次沉积在基片上，因此接触孔的侧壁然后基本上沉积有导电材料。

    Method of manufacturing multilevel metal interconnect
    3.
    发明授权
    Method of manufacturing multilevel metal interconnect 有权
    制造多层金属互连的方法

    公开(公告)号：US6048796A

    公开(公告)日：2000-04-11

    申请号：US211891

    申请日：1998-12-15

    申请人： Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang ,  Chih-Chien Liu ,  Water Lur

    发明人： Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang ,  Chih-Chien Liu ,  Water Lur

    IPC分类号： H01L21/768 ,  H01L21/00

    CPC分类号： H01L21/7684 ,  H01L21/76829

    摘要： A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

    摘要翻译： 描述了一种用于制造多层金属互连的方法。 该方法包括以下步骤：提供衬底，然后在衬底上形成线。 在基板和导线上形成电介质层，在电介质层上形成保护层。 通过图案化保护层和电介质层形成开口，并且在保护层和开口中形成阻挡层。 在阻挡层上形成铜层并填充开口。 通过化学机械抛光去除铜层和阻挡层的一部分。

    Method of fabricating a copper capping layer
    4.
    发明授权
    Method of fabricating a copper capping layer 有权
    铜覆盖层的制造方法

    公开(公告)号：US06339025B1

    公开(公告)日：2002-01-15

    申请号：US09304436

    申请日：1999-04-03

    申请人： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

    发明人： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

    IPC分类号： H01L2144

    CPC分类号： H01L21/76886 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867

    摘要： A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

    摘要翻译： 一种制造铜覆盖层的方法。 在暴露的铜层上形成富氮的氮化物层。 由于富含硅的氮化物层内部具有更多的悬空键，富硅氮化物层中的硅容易与铜反应，并且在铜和富硅氮化物层之间形成铜硅化物层。 因此，可以提高铜和富硅氮化物层的粘合性。

    Chemical plasma treatment for rounding tungsten surface spires
    5.
    发明授权
    Chemical plasma treatment for rounding tungsten surface spires 失效
    化学等离子体处理用于圆形钨表面尖顶

    公开(公告)号：US06180484B2

    公开(公告)日：2001-01-30

    申请号：US09140776

    申请日：1998-08-26

    申请人： Kun-Chih Wang ,  Wen-Yi Hsieh

    发明人： Kun-Chih Wang ,  Wen-Yi Hsieh

    IPC分类号： H01L2120

    CPC分类号： H01L28/60 ,  C23C16/14 ,  C23C16/56 ,  H01L21/7684 ,  H01L21/76877

    摘要： The present invention proposes a method for forming a tungsten film with a good surface property and utilizes a chemical plasma treatment to round the tungsten surface and to improve the leakage issue of tungsten conductive film. A fabrication of a DRAM cell capacitor with tungsten bottom electrode is described for a preferred embodiment. Forming an inter-layer dielectric on a semiconductor substrate, a tungsten layer is formed thereon. A chemical plasma treatment is carried out to round the tungsten surface spires and result in a better surface properties. The tungsten layer is patterned to serve as the bottom electrode, and another dielectric layer is formed to cover the bottom electrode of tungsten. Finally, the top storage electrode is formed to finish the present process.

    摘要翻译： 本发明提出了一种形成具有良好表面性能的钨膜的方法，并利用化学等离子体处理使钨表面圆弧化并改善了钨导电膜的泄漏问题。 对于优选实施例描述了具有钨底电极的DRAM单元电容器的制造。 在半导体衬底上形成层间电介质，在其上形成钨层。 进行化学等离子体处理以使钨表面尖锐化，并产生更好的表面性能。 图案化钨层用作底部电极，并且形成另一个电介质层以覆盖钨的底部电极。 最后，形成顶部存储电极以完成本工艺。

    Method fabricating metal interconnected structure
    6.
    发明授权
    Method fabricating metal interconnected structure 有权
    制造金属互连结构的方法

    公开(公告)号：US06169028A

    公开(公告)日：2001-01-02

    申请号：US09237787

    申请日：1999-01-26

    申请人： Kun-Chih Wang ,  Ming-Sheng Yang ,  Wen-Yi Hsieh

    发明人： Kun-Chih Wang ,  Ming-Sheng Yang ,  Wen-Yi Hsieh

    IPC分类号： H10L2144

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76807

    摘要： A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.

    摘要翻译： 一种制造金属互连结构的方法。 提供了包括其中的导电层的半导体衬底。 在半导体衬底上形成电介质层。 去除介电层的一部分以在其中形成双镶嵌开口和沟槽，其中双镶嵌开口暴露导电层。 沟槽大于双镶嵌开口。 在电介质层上形成保形阻挡层。 在阻挡层上形成保形金属层以填充双镶嵌开口并部分填充沟槽。 定位在沟槽中的金属层的厚度等于沟槽的深度。 在金属层上形成共形盖层。 执行CMP处理以去除沟槽外部的覆盖层，金属层和阻挡层，并且在双镶嵌开口外部。

    Via structure and method of manufacture
    7.
    发明授权
    Via structure and method of manufacture 失效
    通过结构和制造方法

    公开(公告)号：US6080660A

    公开(公告)日：2000-06-27

    申请号：US32682

    申请日：1998-02-27

    申请人： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

    发明人： Kun-Chih Wang ,  Hsiao-Pang Chou ,  Wen-Yi Hsieh ,  Tri-Rung Yew

    IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76805

    摘要： A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

    摘要翻译： 一种用于制造通孔结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上形成导电线和电介质层。 接下来，进行光刻和第一蚀刻操作，从而形成暴露导电线表面的电介质层中的开口。 第一蚀刻操作使用多种蚀刻剂，包括具有最高浓度的氟代丁烷。 由于在开口的底部存在再入口结构，因此进行第二蚀刻操作。 在第二蚀刻操作中，导电线的一部分被蚀刻固定的时间间隔以控制蚀刻程度。 因此，在开口的底部形成倾斜表面，并且消除了再入口结构。 在平坦化的底部，随后沉积材料的阶梯覆盖率增加。

    SCRIBE LINE STRUCTURE
    8.
    发明申请
    SCRIBE LINE STRUCTURE 审中-公开
    可选线结构

    公开(公告)号：US20060022195A1

    公开(公告)日：2006-02-02

    申请号：US10710761

    申请日：2004-08-01

    申请人： Kun-Chih Wang

    发明人： Kun-Chih Wang

    IPC分类号： H01L23/58

    CPC分类号： H01L22/32 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a scribe line structure, which includes a substrate, a plurality of dielectric layers of low dielectric constant materials formed on the substrate, at least a process monitor pattern made of materials of metal formed between the dielectric layers, and a dummy metal structure connected to the process monitor pattern. The dummy metal structure includes a plurality of dummy metal layers and a plurality of dummy vias. The dummy metal structure is formed on the surface of the substrate and is exposed in the region of the scribe line, thus facilitating heat dissipation and energy release from the scribe line structure.

    摘要翻译： 本发明提供一种划片线结构，其包括基板，形成在基板上的多个低介电常数材料的电介质层，至少由形成在电介质层之间的金属材料制成的工艺监视图案，以及虚设金属 结构连接到过程监控模式。 虚拟金属结构包括多个虚拟金属层和多个虚拟通孔。 虚设金属结构形成在基板的表面上，并且在划线的区域中露出，从而有利于散热和从划线结构释放能量。

    Bonding pad structure
    9.
    发明授权
    Bonding pad structure 有权
    粘接垫结构

    公开(公告)号：US06710448B2

    公开(公告)日：2004-03-23

    申请号：US09880518

    申请日：2001-06-12

    申请人： Kun-Chih Wang

    发明人： Kun-Chih Wang

    IPC分类号： H01L2940

    CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

    摘要： A bonding pad structure. The bonding pad structure includes independently built current conduction structure and mechanical support structure between a bonding pad layer and a substrate. The current conduction structure is constructed using a plurality of serially connected conductive metallic layers each at a different height between the bonding pad layer and the substrate. The conductive metallic layers connect with each other via a plurality of plugs. At least one of the conductive metallic layers connects electrically with a portion of the device in the substrate by a signal conduction line. The mechanical support structure is constructed using a plurality of serially connected supportive metallic layers each at a different height between the bonding pad layer and the substrate. The supportive metallic layers connect with each other via a plurality of plugs. Furthermore, the mechanical support structure connects with a non-device section of the substrate so that stresses on the bonding pads are distributed evenly through the substrate.

    摘要翻译： 焊盘结构。 焊盘结构包括独立构建的导电结构和在焊盘层和衬底之间的机械支撑结构。 电流传导结构使用在接合焊盘层和衬底之间的不同高度上的多个串联连接的导电金属层来构造。 导电金属层通过多个插头彼此连接。 至少一个导电金属层通过信号传导线与衬底中的器件的一部分电连接。 机械支撑结构使用多个串联连接的支撑金属层来构造，每个支撑金属层在接合焊盘层和衬底之间的不同高度处。 支撑金属层通过多个插头彼此连接。 此外，机械支撑结构与衬底的非器件部分连接，使得焊盘上的应力均匀地分布在衬底上。