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    DDR receiver enable cycle training
    1.
    发明授权
    DDR receiver enable cycle training 有权
    DDR接收器启用循环训练

    公开(公告)号：US09183125B2

    公开(公告)日：2015-11-10

    申请号：US13330518

    申请日：2011-12-19

    申请人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

    发明人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

    IPC分类号： G11C7/22 ,  G06F12/00 ,  G11C8/18 ,  G06F13/16

    CPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G11C7/222 ,  G11C8/18

    摘要： A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

    摘要翻译： 提供了一种用于对存储器周期的数据选通信号进行采样并基于数据选通信号确定接收器使能相位的方法。 该方法还包括执行存储器写入周期和随后的读取周期，并以四分之一存储器时钟周期性偏移来训练读取数据选通周期。 该方法还包括响应于成功的读数据选通训练周期来确定正确的接收机使能延迟。 还提供计算机可读存储介质。 提供了一种装置，其包括耦合到存储器部分和处理装置的通信接口部分。 该装置还包括耦合到通信接口部分的第一电路部分。 第一电路部分监视通信接口部分上的存储器周期，确定接收器使能周期阶段并训练接收机使能周期，而不使用接收机使能种子。

    DDR RECEIVER ENABLE CYCLE TRAINING
    2.
    发明申请
    DDR RECEIVER ENABLE CYCLE TRAINING 有权
    DDR接收器启用循环培训

    公开(公告)号：US20130159615A1

    公开(公告)日：2013-06-20

    申请号：US13330518

    申请日：2011-12-19

    申请人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

    发明人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

    IPC分类号： G06F12/00 ,  G11C8/18

    CPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G11C7/222 ,  G11C8/18

    摘要： A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

    摘要翻译： 提供了一种用于对存储器周期的数据选通信号进行采样并基于数据选通信号确定接收器使能相位的方法。 该方法还包括执行存储器写入周期和随后的读取周期，并以四分之一存储器时钟周期性偏移来训练读取数据选通周期。 该方法还包括响应于成功的读数据选通训练周期来确定正确的接收机使能延迟。 还提供计算机可读存储介质。 提供了一种装置，其包括耦合到存储器部分和处理装置的通信接口部分。 该装置还包括耦合到通信接口部分的第一电路部分。 第一电路部分监视通信接口部分上的存储器周期，确定接收器使能周期阶段并训练接收机使能周期，而不使用接收机使能种子。

    System and method of data communications between electronic devices
    3.
    发明授权
    System and method of data communications between electronic devices 有权
    电子设备之间数据通信的系统和方法

    公开(公告)号：US08782458B2

    公开(公告)日：2014-07-15

    申请号：US13306680

    申请日：2011-11-29

    申请人： Aaron Nygren ,  Anwar Kashem ,  Edoardo Prete ,  Gerry Talbot

    发明人： Aaron Nygren ,  Anwar Kashem ,  Edoardo Prete ,  Gerry Talbot

    IPC分类号： G06F1/00 ,  G11C7/00

    CPC分类号： G06F13/4243

    摘要： A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.

    摘要翻译： 公开了第一设备和第二设备之间的数据通信的系统和方法。 该方法包括在第一设备处产生第一时钟信号并产生具有与第一时钟信号相位偏移的第二时钟信号。 时钟信号从第一设备发送到第二设备。 该方法还包括利用第一时钟信号来调节从第二设备发送到第一设备的读选通信号的传输。 该方法还包括利用第二时钟信号调节从第二设备发送到第一设备的数据传送信号的传输。

    Method and Apparatus for Memory Access Delay Training
    4.
    发明申请
    Method and Apparatus for Memory Access Delay Training 有权
    存储器访问延迟训练的方法和装置

    公开(公告)号：US20130315014A1

    公开(公告)日：2013-11-28

    申请号：US13477642

    申请日：2012-05-22

    申请人： Glenn A Dearth ,  Warren R. Anderson ,  Anwar P. Kashem ,  Richard W. Reeves ,  Edoardo Prete ,  Gerald E. Talbot

    发明人： Glenn A Dearth ,  Warren R. Anderson ,  Anwar P. Kashem ,  Richard W. Reeves ,  Edoardo Prete ,  Gerald E. Talbot

    IPC分类号： G11C8/18

    CPC分类号： G11C7/22 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

    摘要： Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.

    摘要翻译： 公开了用于训练用于在存储器子系统中启用数据选通信号的延迟的各种方法和装置实施例。 在一个实施例中，系统包括被配置为接收数据选通信号的存储器控​​制器。 存储器控制器包括训练电路。 训练电路包括：第一存储电路，被耦合以在数据输入端接收数据选通信号;以及训练单元，被配置为基于从第一触发器接收的输出信号调整 使能信号的相位直到使能信号的断言与数据选通信号中的前导码指示一致。

    CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE
    5.
    发明申请
    CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE 有权
    用于接收需要第一电源电压的第一电路和需要第二电源电压的第二电源电路的概念

    公开(公告)号：US20080143386A1

    公开(公告)日：2008-06-19

    申请号：US11641545

    申请日：2006-12-19

    申请人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    发明人： Georg Braun ,  Dirk Scheideler ,  Steve Wood ,  Richard Johannes Luyken ,  Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509

    摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

    摘要翻译： 使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。 该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压 可控开关包括电阻元件或与电阻元件分离。 接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。 可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

    Method and apparatus for phase detection
    6.
    发明授权
    Method and apparatus for phase detection 有权
    相位检测方法和装置

    公开(公告)号：US07313211B2

    公开(公告)日：2007-12-25

    申请号：US10407033

    申请日：2003-04-03

    申请人： Peter Gregorius ,  Edoardo Prete ,  Paul Wallner

    发明人： Peter Gregorius ,  Edoardo Prete ,  Paul Wallner

    IPC分类号： H03D3/24

    CPC分类号： H03L7/091 ,  H04L7/0083 ,  H04L7/033

    摘要： The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllable oscillator or a controllable delay device is controlled on the basis of the phase difference determined by means of phase detection, in such a way that a control signal can be obtained, the phase lag or frequency of which has a firm relationship to the reference signal.

    摘要翻译： 本发明涉及根据两个周期信号之间的相位差产生输出信号的方法和装置。 本发明在锁相环和延迟锁定环特别有用，其中基于通过相位检测确定的相位差来控制可控振荡器或可控延迟器件，使得控制信号可以 获得，相位滞后或其频率与参考信号具有牢固的关系。

    METHOD AND APPARATUS FOR USING DFE IN A SYSTEM WITH NON-CONTINUOUS DATA
    7.
    发明申请
    METHOD AND APPARATUS FOR USING DFE IN A SYSTEM WITH NON-CONTINUOUS DATA 有权
    在具有非连续数据的系统中使用DFE的方法和装置

    公开(公告)号：US20120155529A1

    公开(公告)日：2012-06-21

    申请号：US12973242

    申请日：2010-12-20

    申请人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

    发明人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

    IPC分类号： H03K5/159

    CPC分类号： H04L25/03878 ,  H04L25/03057

    摘要： A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

    摘要翻译： 提供了一种判决反馈均衡（DFE）接收机和方法。 DFE接收器配置为从数据总线采样数据位。 DFE接收器包括数据采样器，其被配置为使用第一，第二和第三参考电压之一从数据总线采样当前数据位。 DFE接收机还包括被配置为基于先前的数据总线电平来选择第一，第二和第三电压基准之一的多路复用逻辑。 其中如果先前数据总线电平为逻辑0，则选择第一参考电压。 如果先前的数据总线电平为逻辑1，则选择第二个参考电压。 如果先前的数据总线电平为三态，则选择第三个参考电压。

    Clock signal extraction device and method for extracting a clock signal from data signal
    9.
    发明授权
    Clock signal extraction device and method for extracting a clock signal from data signal 有权
    时钟信号提取装置和从数据信号提取时钟信号的方法

    公开(公告)号：US07532695B2

    公开(公告)日：2009-05-12

    申请号：US10530852

    申请日：2002-10-10

    申请人： Anthony Sanders ,  Edoardo Prete

    发明人： Anthony Sanders ,  Edoardo Prete

    IPC分类号： H03D3/24

    CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033

    摘要： A clock signal extraction device for extracting a clock signal from a periodic data signal includes a phase detector for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal. The device also includes a clock generator for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. A method for extracting a clock signal from a periodic data signal is related to the device.

    摘要翻译： 一种用于从周期性数据信号中提取时钟信号的时钟信号提取装置包括相位检测器，用于检测所述数据信号的上升沿与上升沿时钟信号之间的第一相位差，并且用于检测所述数据信号的下降沿之间的第二相位差 数据信号和下降沿时钟信号。 该装置还包括时钟发生器，用于产生所述上升沿时钟信号，使得所述第一相位差被最小化，用于产生所述下降沿时钟信号，使得所述第二相位差最小化，并且用于根据所述第一相位差产生所述时钟信号 相位差和所述第二相位差。 从周期性数据信号中提取时钟信号的方法与该装置有关。