公开(公告)号：US06772328B1

公开(公告)日：2004-08-03

申请号：US09335939

申请日：1999-06-18

申请人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

发明人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

IPC分类号： G06F15177

CPC分类号： G06F13/4068

摘要： In a common processor module/motherboard interface, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards. A module information field stored on a processor module includes status information pertaining to the processor module. When the processor module is coupled to a motherboard, the motherboard downloads the module information field and generates initialization commands for the processor module based on the retrieved module information field. The commands are transferred to the processor module for initialization of the processor.

摘要翻译： 在通常的处理器模块/主板接口中，定义了一个接口协议，使得替换处理器模块可以被公共主板识别，并且使公共处理器模块可以与多个主板兼容。 存储在处理器模块上的模块信息字段包括与处理器模块有关的状态信息。 当处理器模块耦合到母板时，主板下载模块信息字段，并且基于检索的模块信息字段为处理器模块生成初始化命令。 这些命令被传送到处理器模块，用于处理器的初始化。

公开(公告)号：US09183125B2

公开(公告)日：2015-11-10

申请号：US13330518

申请日：2011-12-19

申请人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

发明人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

IPC分类号： G11C7/22 ,  G06F12/00 ,  G11C8/18 ,  G06F13/16

CPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G11C7/222 ,  G11C8/18

摘要： A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

摘要翻译： 提供了一种用于对存储器周期的数据选通信号进行采样并基于数据选通信号确定接收器使能相位的方法。 该方法还包括执行存储器写入周期和随后的读取周期，并以四分之一存储器时钟周期性偏移来训练读取数据选通周期。 该方法还包括响应于成功的读数据选通训练周期来确定正确的接收机使能延迟。 还提供计算机可读存储介质。 提供了一种装置，其包括耦合到存储器部分和处理装置的通信接口部分。 该装置还包括耦合到通信接口部分的第一电路部分。 第一电路部分监视通信接口部分上的存储器周期，确定接收器使能周期阶段并训练接收机使能周期，而不使用接收机使能种子。

公开(公告)号：US20130155788A1

公开(公告)日：2013-06-20

申请号：US13330460

申请日：2011-12-19

申请人： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

发明人： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

摘要： A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

公开(公告)号：US20050166006A1

公开(公告)日：2005-07-28

申请号：US10842298

申请日：2004-05-10

申请人： Gerald Talbot ,  Frederick Weber ,  Shwetal Patel

发明人： Gerald Talbot ,  Frederick Weber ,  Shwetal Patel

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/28 ,  G11C5/00

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, at least one of the memory modules includes a cache for storing data stored in a system memory.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，至少一个存储器模块包括用于存储存储在系统存储器中的数据的高速缓存。

公开(公告)号：US06516373B1

公开(公告)日：2003-02-04

申请号：US09335954

申请日：1999-06-18

申请人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

发明人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

IPC分类号： G06F1300

CPC分类号： G06F13/4068

摘要： A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

摘要翻译： 通用的主板接口可容纳不同处理器架构的处理器模块。 该系统包括用于与插入主板的处理器模块通信的接口。 该接口从处理器模块接收标识符信号。 标识符信号标识处理器模块体系结构。 架构选择电路基于标识符信号选择性地与处理器模块交换处理器架构特定信号。 以这种方式，具有完全不同的处理器架构的多个处理器模块可以共享公共主板，从而提供可以由不同架构的处理器模块进行现场升级的系统，或者简单地允许将相同的主板用于两种不同的产品 的不同处理器架构。

公开(公告)号：US08850155B2

公开(公告)日：2014-09-30

申请号：US13330460

申请日：2011-12-19

申请人： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

发明人： Kevin M. Brandl ,  Oswin E. Housty ,  Gerald Talbot

IPC分类号： G06F13/00

CPC分类号： G11C7/00 ,  G06F3/0614 ,  G06F3/0653 ,  G06F12/16 ,  G06F13/1689 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028

摘要： A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

摘要翻译： 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。

公开(公告)号：US20070208819A1

公开(公告)日：2007-09-06

申请号：US11368785

申请日：2006-03-06

申请人： Gerald Talbot ,  R. Polzin

发明人： Gerald Talbot ,  R. Polzin

IPC分类号： G06F15/16

CPC分类号： H04L1/0026 ,  H04L1/0061 ,  H04L1/205 ,  H04L1/243 ,  H04L25/03006 ,  H04L2001/0094

摘要： A system including asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths, for example. The master device may control data transfer between the master device and the slave device. More particularly, the master device may adaptively modify transmit characteristics subsequent to adaptively modifying receiver characteristics based upon information received from the slave device via one or more unidirectional data paths.

摘要翻译： 包括高速双向信令的不对称控制的系统包括例如从属设备和通过多个双向数据路径耦合到从设备的主设备。 主设备可以控制主设备和从设备之间的数据传输。 更具体地，主设备可以基于经由一个或多个单向数据路径从从设备接收到的信息自适应地修改接收机特性。

公开(公告)号：US06865682B1

公开(公告)日：2005-03-08

申请号：US09335940

申请日：1999-06-18

申请人： Gerald Talbot ,  Hanwoo Cho

发明人： Gerald Talbot ,  Hanwoo Cho

IPC分类号： G06F1/26 ,  H05K1/02 ,  H05K1/14 ,  G05F1/02 ,  G06F13/00

CPC分类号： G06F1/26 ,  H05K1/0254 ,  H05K1/141

摘要： In a microprocessor module assembly, voltage regulators are integrated into the module and adapted for use with a processor and support electronics likewise mounted on the module. The voltage regulators receive a fixed imput voltage from a motherboard interface and provide modified regulated output voltages to the processor and support electronics. In this manner, the processor module is readily upgradable such that future generations are compatible with a fixed motherboard interface without the need for upgrading voltage regulators on the motherboard. In a preferred embodiment, bulk decoupling capacitance is provided on the processor assembly to stabilize the DC output voltage of the voltage regulators.

摘要翻译： 在微处理器模块组件中，电压调节器集成到模块中并适用于同样安装在模块上的处理器和支撑电子装置。 电压调节器从主板接口接收固定的输入电压，并向处理器和支持电子设备提供修改的稳压输出电压。 以这种方式，处理器模块易于升级，使得后代与固定的主板接口兼容，而不需要升级主板上的稳压器。 在优选实施例中，体解耦电容被提供在处理器组件上以稳定稳压器的DC输出电压。

公开(公告)号：US20130159615A1

公开(公告)日：2013-06-20

申请号：US13330518

申请日：2011-12-19

申请人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

发明人： Kevin M. Brandl ,  Oswin E. Housty ,  Edoardo Prete ,  Gerald Talbot

IPC分类号： G06F12/00 ,  G11C8/18

CPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/1689 ,  G11C7/222 ,  G11C8/18

摘要： A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

摘要翻译： 提供了一种用于对存储器周期的数据选通信号进行采样并基于数据选通信号确定接收器使能相位的方法。 该方法还包括执行存储器写入周期和随后的读取周期，并以四分之一存储器时钟周期性偏移来训练读取数据选通周期。 该方法还包括响应于成功的读数据选通训练周期来确定正确的接收机使能延迟。 还提供计算机可读存储介质。 提供了一种装置，其包括耦合到存储器部分和处理装置的通信接口部分。 该装置还包括耦合到通信接口部分的第一电路部分。 第一电路部分监视通信接口部分上的存储器周期，确定接收器使能周期阶段并训练接收机使能周期，而不使用接收机使能种子。

公开(公告)号：US06259600B1

公开(公告)日：2001-07-10

申请号：US09334982

申请日：1999-06-17

申请人： Gerald Talbot ,  Michael Beale ,  Michael Reynolds

发明人： Gerald Talbot ,  Michael Beale ,  Michael Reynolds

IPC分类号： H05K720

CPC分类号： H05K7/1431 ,  G06F1/20

摘要： A structure and method for mounting a processor assembly on a mother board and a structure and method for cooling the processor assembly are described. The processor assembly includes a processor circuit board assembly which is located adjacent to a heat sink for removing heat from the circuit board assembly. The heat sink and circuit board assembly are maintained in an upright position with respect to the mother board by a fame mounted on the mother board and/or the computer system chassis. A cover mounted to the top of the frame holds a connector on the processor circuit board assembly in mating contact with a connector on the mother board. The cover also serves to complete an enclosure around the heat sink and processor circuit board assembly. Fans mounted to the frame move air from an intake end of the processor assembly, across cooling fins on the heat sink, to an outlet end of the processor assembly such that a ducted cooling system is provided for the processor assembly.

摘要翻译： 描述了一种用于将处理器组件安装在母板上的结构和方法以及用于冷却处理器组件的结构和方法。 处理器组件包括位于与散热器相邻的处理器电路板组件，用于从电路板组件移除热量。 散热器和电路板组件通过安装在母板和/或计算机系统底盘上的名声相对于母板保持在直立位置。 安装到框架顶部的盖子将处理器电路板组件上的连接器保持与母板上的连接器配合接触。 盖子还用于完成散热器和处理器电路板组件周围的外壳。 安装在框架上的风扇将空气从处理器组件的进气端移动到散热器上的散热片上，从而将处理器组件的管道冷却系统提供给处理器组件。