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11 条记录 (耗时 0.022 秒)

    Conformal electroless deposition of barrier layer materials
    1.
    发明申请
    Conformal electroless deposition of barrier layer materials 有权
    阻挡层材料的保形无电沉积

    公开(公告)号：US20070148952A1

    公开(公告)日：2007-06-28

    申请号：US11318137

    申请日：2005-12-23

    申请人： Kevin O'Brien ,  Chin-Chang Cheng ,  Ramanan Chebiam ,  Valery Dubin ,  Sridhar Balakrishnan

    发明人： Kevin O'Brien ,  Chin-Chang Cheng ,  Ramanan Chebiam ,  Valery Dubin ,  Sridhar Balakrishnan

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  B82Y30/00 ,  H01L21/288 ,  H01L21/76874

    摘要： Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.

    摘要翻译： 使用利用与催化金属复合的偶联剂和由此形成的结构的化学沉积技术形成的阻挡材料层来制造互连结构的方法。 该制造基本上包括提供介电材料层，其具有从其第一表面延伸到电介质材料中的开口，将该耦合剂粘合到该开口内的电介质材料，以及无电沉积阻挡材料层，其中该无电沉积阻挡材料层 材料粘附到偶联剂的催化金属上。

    Method for making a semiconductor device having increased conductive material reliability
    4.
    发明申请
    Method for making a semiconductor device having increased conductive material reliability 有权
    制造具有增加的导电材料可靠性的半导体器件的方法

    公开(公告)号：US20050090098A1

    公开(公告)日：2005-04-28

    申请号：US10695249

    申请日：2003-10-27

    申请人： Valery Dubin ,  Ramanan Chebiam

    发明人： Valery Dubin ,  Ramanan Chebiam

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

    摘要翻译： 描述了具有导电材料可靠性增加的半导体器件的半导体器件的方法和装置。 该方法和装置包括在衬底上形成导电路径。 由第一材料制成的导电路径。 然后将第二材料沉积在导电路径上。 一旦第二材料沉积在导电路径上，则促进了第二材料进入导电路径的扩散。 第二材料具有预定的溶解度以基本上扩散到第一材料内的晶界。

    METAL INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES
    7.
    发明申请
    METAL INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES 审中-公开
    金属互连结构的半导体器件

    公开(公告)号：US20090166867A1

    公开(公告)日：2009-07-02

    申请号：US11968139

    申请日：2007-12-31

    申请人： Harsono Simka ,  Sadasivan Shankar ,  Michael Haverty ,  Ramanan Chebiam ,  Florian Gstrein

    发明人： Harsono Simka ,  Sadasivan Shankar ,  Michael Haverty ,  Ramanan Chebiam ,  Florian Gstrein

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76874 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

    摘要： Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described.

    摘要翻译： 在本申请中描述了使用无底衬管以减少铜界面电子散射并降低电阻的Cu互连结构。 互连结构包括可以由氧化物或氮化物形成的成核层和衬里层。 去除衬里层的底部以露出成核层。 由于衬垫是无底的，所以成核层在Cu沉积期间被暴露，并且用于催化铜成核并使底部（其中成核层被暴露）附近的铜的选择性生长，而不是靠近衬里侧壁。 因此，铜可以以自下而上的填充行为选择性地生长，可以减少或消除空隙的形成。 描述其他实施例。

    Reducing electrical resistance in electrolessly deposited copper interconnects
    9.
    发明申请
    Reducing electrical resistance in electrolessly deposited copper interconnects 审中-公开
    在无电沉积的铜互连中降低电阻

    公开(公告)号：US20070065585A1

    公开(公告)日：2007-03-22

    申请号：US11233297

    申请日：2005-09-21

    申请人： Ramanan Chebiam ,  Arnel Fajardo

    发明人： Ramanan Chebiam ,  Arnel Fajardo

    IPC分类号： B05D1/32 ,  B05D3/04

    CPC分类号： C23C18/165 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/182 ,  C23C18/1841 ,  C23C18/1844 ,  C23C18/1868 ,  C23C18/1889 ,  C23C18/1893 ,  H01L21/288 ,  H01L21/76874 ,  H01L21/76877 ,  H05K3/185 ,  H05K3/389

    摘要： A method of forming an electrolessly deposited copper interconnect while reducing its electrical resistance comprises providing a substrate having a dielectric layer, wherein a trench portion including at least two sidewall surfaces and a bottom surface is etched into the dielectric layer, depositing a copper seed layer onto the substrate and within the trench portion, attaching a layer of a metal catalyst to the substrate and within the trench portion using a coupling agent, applying ultraviolet radiation to the trench portion to detach the metal catalyst from the sidewall surfaces and the bottom surface of the trench portion, activating the metal catalyst that remains attached to the substrate, performing an electroless plating process to deposit copper into the trench portion, and planarizing the deposited copper to form an interconnect. The result is a copper interconnect that is not contaminated with a metal catalyst that may increase its electrical resistance.

    摘要翻译： 一种形成无电沉积铜互连同时降低其电阻的方法包括提供具有电介质层的衬底，其中包括至少两个侧壁表面和底表面的沟槽部分被蚀刻到电介质层中，将铜籽晶层沉积到 衬底，并且在沟槽部分内，使用耦合剂将金属催化剂层附着到衬底和沟槽部分内，向沟槽部分施加紫外线辐射以将金属催化剂从侧壁表面和底表面分离 激活保持附着于基板的金属催化剂，进行化学镀处理以将铜沉积到沟槽部分中，以及平坦化沉积的铜以形成互连。 结果是铜互连不被可能增加其电阻的金属催化剂污染。

    SELECTIVE ELECTROLESS METAL DEPOSITION FOR DUAL SALICIDE PROCESS
    10.
    发明申请
    SELECTIVE ELECTROLESS METAL DEPOSITION FOR DUAL SALICIDE PROCESS 审中-公开
    选择性电解金属沉积双重杀菌工艺

    公开(公告)号：US20090315185A1

    公开(公告)日：2009-12-24

    申请号：US12143248

    申请日：2008-06-20

    申请人： Boyan Boyanov ,  Ramanan Chebiam

    发明人： Boyan Boyanov ,  Ramanan Chebiam

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/823814

    摘要： A method for forming dual salicide contacts includes depositing a low or mid-gap work function metal selectively on an NMOS source/drain (S/D) region of a semiconductor device via electroless deposition; depositing a high work function metal selectively over the low work function metal and a PMOS source/drain (S/D) region of a semiconductor device via electroless deposition; annealing the semiconductor device to form a silicide of the low work function metal over the NMOS source/drain (S/D) region and a silicide of the high work function metal over the PMOS source/drain (S/D) region; and performing a SALICIDE etch to remove the unreacted metals from all regions of the substrate.

    摘要翻译： 一种用于形成双重硅化物接触的方法包括通过无电沉积在半导体器件的NMOS源极/漏极（S / D）区域上选择性地沉积低或中间功函数金属; 通过无电沉积在半功能金属和半导体器件的PMOS源极/漏极（S / D）区域上选择性地沉积高功函数金属; 对半导体器件进行退火，以在NMOS源极/漏极（S / D）区域上形成低功函数金属的硅化物，并在PMOS源极/漏极（S / D）区域上形成高功函数金属的硅化物; 并进行SICICIDE蚀刻以从基底的所有区域去除未反应的金属。