公开(公告)号：US5405801A

公开(公告)日：1995-04-11

申请号：US25421

申请日：1993-03-01

申请人： Ki-man Han ,  Chang-gyu Hwang ,  Dug-dong Kang ,  Young-Jae Choi ,  Joo-young Yoon

发明人： Ki-man Han ,  Chang-gyu Hwang ,  Dug-dong Kang ,  Young-Jae Choi ,  Joo-young Yoon

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/32155 ,  H01L27/10808 ,  H01L28/84 ,  H01L29/66181 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/016 ,  Y10S148/138

摘要： A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.

摘要翻译： 公开了一种用于制造半导体器件的电容器的第一电极的方法。 在形成由具有微观结构的晶粒构成的多晶层，在其中含有杂质的情况下，蚀刻多晶层以切割晶粒的边界部分，从而使多晶层的表面变得坚固。 通过在暴露第一坚固多晶层的表面之后使用氧化物层或各向异性蚀刻形成微沟槽或微柱，并且通过外延生长形成外延晶粒，从而可以进一步增加电池电容。 简单的过程允许形成具有规则性和再现性的可靠的半导体器件，并且能够容易地增加和调整电池电容。

公开(公告)号：US5491103A

公开(公告)日：1996-02-13

申请号：US225287

申请日：1994-04-08

申请人： Tae-hyuk Ahn ,  In-ho Nam ,  Joo-young Yoon

发明人： Tae-hyuk Ahn ,  In-ho Nam ,  Joo-young Yoon

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817

摘要： A method for manufacturing a capacitor structure of a highly integrated semiconductor memory device. A first conductive layer is formed on a semiconductor substrate, and a first pattern is formed on the first conductive layer. A first material layer is formed on the resultant structure whereon the first pattern is formed, and the first material layer is etched anisotropically, to thereby form a spacer on the side of the first pattern. After etching the first conductive layer using the spacer as an etch-mask, the first pattern is removed. A second conductive layer is formed on the resultant structure and etched anisotropically. The spacer is removed, to thereby form a storage electrode of a capacitor. The distance between neighboring capacitors can be minimized to a value smaller than the limitation imposed by the lithographic technique, to thereby maximize the area of the capacitor.

摘要翻译： 一种用于制造高度集成的半导体存储器件的电容器结构的方法。 第一导电层形成在半导体衬底上，第一图案形成在第一导电层上。 第一材料层形成在其上形成第一图案的所得结构上，并且第一材料层被各向异性地蚀刻，从而在第一图案侧形成间隔物。 在使用间隔物蚀刻第一导电层作为蚀刻掩模之后，第一图案被去除。 在所得结构上形成第二导电层并各向异性地进行蚀刻。 去除间隔物，从而形成电容器的存储电极。 相邻电容器之间的距离可以最小化为小于由光刻技术施加的限制的值，从而使电容器的面积最大化。

公开(公告)号：US5620917A

公开(公告)日：1997-04-15

申请号：US615087

申请日：1996-03-14

申请人： Joo-young Yoon ,  In-ho Nam

发明人： Joo-young Yoon ,  In-ho Nam

IPC分类号： H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： In a semiconductor memory device having a novel structure of a wiring layer and a large capacitance capacitor and the manufacturing method therefor, on the transistor formed on the semiconductor substrate, a first conductive layer is formed extending along with the gate electrode of the transistor and connecting with the gate electrode, a storage electrode of a capacitor is formed on the first conductive layer by interposing the insulation film between the first conductive layer and the source region of the transistor, and a second conductive layer is formed in connection with the first conductive layer at a portion between memory cell array and the peripheral circuit region. Storage electrodes can be made thicker without affecting to the step-difference between memory cells and the peripheral circuit region, so that a more reliable semiconductor memory device with a capacitor having a larger capacitance can be realized.

摘要翻译： 在具有布线层和大容量电容器的新颖结构的半导体存储器件及其制造方法中，在形成在半导体衬底上的晶体管上形成有与晶体管的栅电极一起延伸的第一导电层， 通过在第一导电层和晶体管的源极区域之间插入绝缘膜，在第一导电层上形成电容器的存储电极，并且与第一导电层形成第二导电层 在存储单元阵列和外围电路区域之间的部分。 可以使存储电极变得更厚，而不会影响存储单元和外围电路区域之间的差分，从而可以实现具有较大电容的电容器的更可靠的半导体存储器件。

公开(公告)号：US06338051B1

公开(公告)日：2002-01-08

申请号：US09301317

申请日：1999-04-29

申请人： Ho-seok Kang ,  Sun-wha Chung ,  Kwang-hyung Lee ,  Joo-young Yoon ,  Kyoung-a Sung

发明人： Ho-seok Kang ,  Sun-wha Chung ,  Kwang-hyung Lee ,  Joo-young Yoon ,  Kyoung-a Sung

IPC分类号： G06F1518

CPC分类号： G06Q30/02

摘要： A user preference modeling method using fuzzy networks. The user preference modeling method includes the steps of: (a) changing a user modeling structure into a fuzzy network structure in which a plurality of layers including one or more graphs with one or more nodes are stacked; (b) when information is input from a user, searching a node directly associated with the input information on the fuzzy networks, and calculating a new preference for the node with a predetermined equation; (c) calculating connection strengths among each node in a graph to which the node belongs according to the new preference obtained in step (b) and calculating a new preference for each node of the graph according to the connection strengths; (d) when a node of the graph to which the node searched in step (b) belongs is a macro node of a graph of a lower layer, and a node is defined as the macro node if a graph of a lower layer defines sub-regions of the node, transferring a first message as preference change information from the macro node to the graph of the lower layer; (e) when the graph to which the node searched in step (b) belongs has a macro node in an upper layer, transferring a second message to the macro node, as preference change information for all nodes of the graph to which the node belongs; (f) when a graph receives the first message from a macro node, calculating a new preference for all nodes in the graph that has received the first message, and when a node of the graph that has received the first message is a macro node of a graph of a lower layer, transferring a first message as preference change information to the graph of the lower layer; and (g) when a node receives the second message from a graph of a lower layer, calculating a new preference for the node that has received the second message and performing steps (c) through (e) to other nodes.

摘要翻译： 一种使用模糊网络的用户偏好建模方法。 用户偏好建模方法包括以下步骤：（a）将用户建模结构改变为模糊网络结构，其中包括具有一个或多个节点的一个或多个图形的多个层被堆叠; （b）当从用户输入信息时，搜索与所述模糊网络上的输入信息直接相关联的节点，并且以预定方程计算所述节点的新偏好; （c）根据步骤（b）中获得的新偏好计算节点所属的图中每个节点之间的连接强度，并根据连接强度计算图的每个节点的新偏好; （d）当在步骤（b）中搜索到的节点所属的图的节点是下层的图的宏节点时，如果下层的图定义子节点，则将节点定义为宏节点 所述节点的区域，将第一消息作为偏好改变信息从所述宏节点转移到所述下层的图形; （e）当在步骤（b）中搜索的节点所属的图形具有上层的宏节点时，将第二消息传送到宏节点作为节点所属图形的所有节点的偏好改变信息 ; （f）当图形从宏节点接收到第一消息时，计算已经接收到第一消息的图中所有节点的新偏好，并且当接收到第一消息的图的节点是 下层的图形，将第一消息作为偏好改变信息传送到下层的图形; 以及（g）当节点从较低层的图形接收到第二消息时，计算已经接收到第二消息的节点的新偏好，并且执行步骤（c）至（e）到其他节点。

公开(公告)号：US5583356A

公开(公告)日：1996-12-10

申请号：US158851

申请日：1993-11-29

申请人： Joo-young Yoon ,  In-ho Nam

发明人： Joo-young Yoon ,  In-ho Nam

IPC分类号： H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： In a semiconductor memory device having a novel structure of a wiring layer and a large capacitance capacitor and the manufacturing method therefor, on the transistor formed on the semiconductor substrate, a first conductive layer is formed extending along with the gate electrode of the transistor and connecting with the gate electrode, a storage electrode of a capacitor is formed on the first conductive layer by interposing the insulation film between the first conductive layer and the source region of the transistor, and a second conductive layer is formed in connection with the first conductive layer at a portion between memory cell array and the peripheral circuit region. Storage electrodes can be made thicker without affecting to the step-difference between memory cells and the peripheral circuit region, so that a more reliable semiconductor memory device with a capacitor having a larger capacitance can be realized.

摘要翻译： 在具有布线层和大容量电容器的新颖结构的半导体存储器件及其制造方法中，在形成在半导体衬底上的晶体管上形成有与晶体管的栅电极一起延伸的第一导电层， 通过在第一导电层和晶体管的源极区域之间插入绝缘膜，在第一导电层上形成电容器的存储电极，并且与第一导电层形成第二导电层 在存储单元阵列和外围电路区域之间的部分。 可以使存储电极变得更厚，而不会影响存储单元和外围电路区域之间的差分，从而可以实现具有较大电容的电容器的更可靠的半导体存储器件。