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公开(公告)号：US11335388B2
公开(公告)日：2022-05-17
申请号：US16862893
申请日：2020-04-30
Applicant: KIOXIA CORPORATION
Inventor： Hiroki Date
IPC: G11C7/22 , H01L27/11582 , H01L27/1157 , H01L27/11573 , G11C16/28 , G11C16/08 , G11C16/32 , G11C16/10 , H01L27/11556 , H01L27/11524 , H01L27/11526
Abstract: In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a command to stop is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.
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公开(公告)号：US11749348B2
公开(公告)日：2023-09-05
申请号：US17412383
申请日：2021-08-26
Applicant: Kioxia Corporation
Inventor： Hiroki Date
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C16/3459 , H10B69/00
Abstract: A semiconductor storage device includes: a plurality of first memory cells; a word line connected to gates of the first memory cells; a voltage generation circuit configured to generate voltage to be supplied to the word line on the basis of a set value; and a control unit configured to execute a write sequence that includes a plurality of loops, each loop including a program operation to increase a threshold voltage of at least part of the first memory cells to thereby write data to the first memory cells and a verify operation to verify the data written to the first memory cells. The voltage generation circuit generates voltage to be supplied to the word line at start of the verify operation on the basis of a first set value, and the control unit adjusts the first set value in accordance with progress of the write sequence.
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公开(公告)号：US12051483B2
公开(公告)日：2024-07-30
申请号：US17729114
申请日：2022-04-26
Applicant: Kioxia Corporation
Inventor： Hiroki Date
IPC: G11C7/22 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/32 , H10B43/27 , H10B43/35 , H10B43/40 , H10B41/27 , H10B41/35 , H10B41/40
CPC classification number: G11C7/22 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/32 , H10B43/27 , H10B43/35 , H10B43/40 , H10B41/27 , H10B41/35 , H10B41/40
Abstract: In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a stop command is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.
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公开(公告)号：US12014773B2
公开(公告)日：2024-06-18
申请号：US17882128
申请日：2022-08-05
Applicant: Kioxia Corporation
Inventor： Hiroki Date , Takeshi Nakano
CPC classification number: G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/26 , H10B41/27 , H10B43/27
Abstract: A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.
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Patent Agency Ranking
公开(公告)号：US11238941B2
公开(公告)日：2022-02-01
申请号：US17007691
申请日：2020-08-31
Applicant: Kioxia Corporation
Inventor： Hiroki Date
IPC: G11C16/04 , G11C16/26 , G11C16/34 , G11C16/32 , G11C16/08 , G11C16/10 , H01L25/18 , H01L27/11582 , H01L27/11565
Abstract: A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.
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公开(公告)号：US12027208B2
公开(公告)日：2024-07-02
申请号：US17680143
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Hiroki Date
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/26
Abstract: A semiconductor memory device includes a memory cell array, a decoder circuit, a voltage supply circuit, and a control circuit. The voltage supply circuit is configured to generate a first voltage supplied to the decoder circuit, a second voltage supplied to a select gate line, and a third voltage supplied to a word line. The control circuit, during a read operation with respect to a memory cell transistor, starts a first control operation on the voltage supply circuit to boost the first voltage to a first target voltage, during the first control operation, starts a second control operation to boost the second voltage, and during the second control operation, starts a third control operation to boost the third voltage. During the first control operation, the first voltage is increased to and maintained at an intermediate voltage lower than the first target voltage for a certain period of time.
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公开(公告)号：US11869597B2
公开(公告)日：2024-01-09
申请号：US17464297
申请日：2021-09-01
Applicant: Kioxia Corporation
Inventor： Takeshi Nakano , Yuzuru Shibazaki , Hideyuki Kataoka , Junichi Sato , Hiroki Date
CPC classification number: G11C16/102 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/30 , G11C29/42
Abstract: A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.
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公开(公告)号：US11450383B2
公开(公告)日：2022-09-20
申请号：US17183933
申请日：2021-02-24
Applicant: Kioxia Corporation
Inventor： Hiroki Date , Takeshi Nakano
IPC: G11C16/26 , G11C11/56 , G11C16/04 , H01L27/11582 , H01L27/11556
Abstract: A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line.
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公开(公告)号：US10984858B2
公开(公告)日：2021-04-20
申请号：US16785752
申请日：2020-02-10
Applicant: Kioxia Corporation
Inventor： Hiroki Date
Abstract: A semiconductor storage device includes: a voltage generation circuit configured to generate a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected and a read-pass voltage to be supplied to an adjacent word line; a word line driver configured to, when the read voltage transitions, apply the read voltage to the selected word line with a first kick voltage amount and apply the read-pass voltage to the adjacent word line with a second kick voltage amount; and a control circuit configured to set each of the first kick voltage amount and the second kick voltage amount to a voltage corresponding to an amount of the transition.
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