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    Semiconductor memory device permitting high speed data transfer and high density integration
    3.
    发明授权
    Semiconductor memory device permitting high speed data transfer and high density integration 失效
    半导体存储器件允许高速数据传输和高密度集成

    公开(公告)号：US5586076A

    公开(公告)日：1996-12-17

    申请号：US304899

    申请日：1994-09-13

    申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Kiyohiro Furutani ,  Shigeru Kikuda

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/24

    CPC分类号： G11C11/4096 ,  G11C7/10

    摘要： In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

    摘要翻译： 在存储单元阵列中，数据线被形成为每个块提供的子数据线和每个块共同的主数据线的分层布置，以及由属于块的子数据线之间的列地址选择的子数据线 通过行地址同时选择连接到位线。 因此，减少了子数据线的长度，这降低了浮动电容，可以高速地执行读和写操作，并且可以选择性地操作子数据线。 此外，可以减少对子数据线进行充电所需的功率，并且可以减小半导体存储器件的整体功耗。

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5519243A

    公开(公告)日：1996-05-21

    申请号：US305524

    申请日：1994-09-13

    申请人： Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    发明人： Shigeru Kikuda ,  Kiyohiro Furutani ,  Makoto Suwa

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L29/76 ,  H01L21/265

    CPC分类号： H01L27/105 ,  Y10S438/901

    摘要： A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

    摘要翻译： 根据本发明的半导体器件在p基板的主表面上包括存储电路区域和外围电路区域。 n阱围绕包括存储电路区域的p阱和包括外围电路区域的p阱。 结果，在半导体衬底中形成电容元件。 可以使半导体器件小型化，并提高元件之间的连接的可靠性。

    Semiconductor memory device with IO compression test mode
    5.
    发明授权
    Semiconductor memory device with IO compression test mode 失效
    半导体存储器件具有IO压缩测试模式

    公开(公告)号：US06301169B1

    公开(公告)日：2001-10-09

    申请号：US09658011

    申请日：2000-09-08

    申请人： Shigeru Kikuda ,  Takeshi Hamamoto ,  Mikio Asakura

    发明人： Shigeru Kikuda ,  Takeshi Hamamoto ,  Mikio Asakura

    IPC分类号： G11C700

    CPC分类号： G11C7/1006 ,  G11C29/40

    摘要： In a set of memory cells selected by one column select line, a memory cell of at least 1 bit is connected to an internal data line that is different from the internal data line to which another memory cell in the same set is connected. An internal data line pair is connected to a data terminal. Thus, data having different logic levels can be written into adjacent memory cells even in an IO compression test mode.

    摘要翻译： 在由一列选择线选择的一组存储器单元中，至少1位的存储单元连接到内部数据线，该内部数据线与同一组中的另一个存储单元连接到的内部数据线不同。 内部数据线对连接到数据终端。 因此，即使在IO压缩测试模式下，也可以将具有不同逻辑电平的数据写入相邻存储单元。

    Semiconductor circuit device having multiplex selection functions
    6.
    发明授权
    Semiconductor circuit device having multiplex selection functions 失效
    具有多重选择功能的半导体电路设备

    公开(公告)号：US5227997A

    公开(公告)日：1993-07-13

    申请号：US708027

    申请日：1991-05-31

    申请人： Shigeru Kikuda ,  Takeshi Hamamoto

    发明人： Shigeru Kikuda ,  Takeshi Hamamoto

    IPC分类号： G11C11/418 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00

    CPC分类号： G11C29/808 ,  G11C29/84

    摘要： The semiconductor circuit device includes a first column decoder for decoding an internal column address and generating a column select signal which selects one column, and a second column decoder for simultaneously selecting a plurality of successively adjacent columns from a memory cell array in accordance with the column select signal. The second column decoder selects the same column in a duplicated way in response to different column select signals. Since the same column is selected in a duplicate way by the different column select signals, it will be possible to simultaneously select a desired combination of a plurality of columns. A combination of a plurality of columns simultaneously selected can be arbitrarily set and a desired combination of columns can be selected with a simplified circuit structure at high speed. It will be possible to repair a column containing a defective bit without providing a redundant column by providing an input/output control circuit for further selecting a column from the columns simultaneously selected in accordance with the column select signal.

    摘要翻译： 半导体电路装置包括用于对内部列地址进行解码并产生选择一列的列选择信号的第一列解码器，以及第二列解码器，用于根据该列从存储单元阵列中同时选择多个相继的相邻列 选择信号。 第二列解码器以复制方式响应于不同的列选择信号选择相同的列。 由于通过不同的列选择信号以重复的方式选择相同的列，所以可以同时选择多个列的所需组合。 同时选择的多个列的组合可以任意设置，并且可以利用简单的电路结构高速选择列的期望组合。 通过提供输入/输出控制电路，可以根据列选择信号从同时选择的列进一步选择列，来修复包含有缺陷位的列而不提供冗余列。

    Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode
    7.
    发明授权
    Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode 失效
    具有快速数据写入模式的半导体存储器件和以快速数据写入模式写入测试数据的方法

    公开(公告)号：US5903575A

    公开(公告)日：1999-05-11

    申请号：US158837

    申请日：1993-11-29

    申请人： Shigeru Kikuda

    发明人： Shigeru Kikuda

    IPC分类号： G11C29/00 ,  G01R31/28 ,  G11C11/401 ,  G11C29/10 ,  G11C29/24 ,  G11C29/34 ,  H01L27/10

    CPC分类号： G11C29/24

    摘要： Disclosed is a semiconductor memory device including a normal memory array and preliminary memory array enabling a mutual data transfer. Word lines in the normal memory array and those in the preliminary memory array are controlled by separate row decoders and separate word drivers. Bit lines and sense amplifiers are provided commonly to the normal memory array and the preliminary memory array. When test data is written in a predetermined pattern into the normal memory array, data corresponding to the predetermined pattern is written in advance for each memory cell in the preliminary memory array. Then, after the row decoder and word driver for the preliminary memory array are enabled so that the word lines in the preliminary memory array are activated, the row decoder and word driver for the normal memory array are enabled so that the word lines in the preliminary memory array are activated. Thus, data signals read from memory cells of one row in the normal memory array are simultaneously amplified by the sense amplifiers via the bit lines and then transferred via the bit lines to memory cells of one row in the preliminary memory array. In this result, the test data are written at one time into the memory cells of one row in the normal memory array.

    摘要翻译： 公开了一种包括正常存储器阵列和能够进行相互数据传输的初步存储器阵列的半导体存储器件。 正常存储器阵列中的字线和初步存储器阵列中的字线由单独的行解码器和单独的字驱动器控制。 位线和读出放大器通常提供给正常存储器阵列和初步存储器阵列。 当以预定图案将测试数据写入正常存储器阵列中时，预备存储器阵列中的每个存储单元预先写入与预定图案对应的数据。 然后，在初步存储器阵列的行解码器和字驱动器被使能以使得初步存储器阵列中的字线被激活之后，启用用于正常存储器阵列的行解码器和字驱动器，使得初步存储器阵列中的字线 存储器阵列被激活。 因此，从正常存储器阵列中的一行的存储单元读取的数据信号经由位线被读出放大器同时放大，然后经由位线被传送到预备存储器阵列中的一行的存储单元。 在该结果中，将测试数据一次写入正常存储器阵列中的一行的存储单元。

    Semiconductor device having no through current flow in standby period
    8.
    发明授权
    Semiconductor device having no through current flow in standby period 失效
    半导体器件在待机期间没有通过电流流动

    公开(公告)号：US5321654A

    公开(公告)日：1994-06-14

    申请号：US863975

    申请日：1992-04-06

    申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C5/14 ,  G11C8/18

    摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

    摘要翻译： 一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。 该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。 响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。 在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

    Dynamic random access memory having storage gate electrode grounding means
    9.
    发明授权
    Dynamic random access memory having storage gate electrode grounding means 失效
    具有存储栅电极接地装置的动态随机存取存储器

    公开(公告)号：US4879679A

    公开(公告)日：1989-11-07

    申请号：US163017

    申请日：1988-03-02

    申请人： Shigeru Kikuda ,  Hiroshi Miyamoto

    发明人： Shigeru Kikuda ,  Hiroshi Miyamoto

    IPC分类号： G11C11/404 ,  G11C11/4072 ,  G11C11/4074 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C11/4074 ,  G11C11/4072 ,  Y10T307/281

    摘要： A dynamic RAM provided on a semiconductor substrate comprises: a memory cell including a capacitor for storing electric charges as information, the capacitor having a storage gate electrode to which a potential other than a ground potential is applied during normal operation of the dynamic RAM; a peripheral circuit including a CMOS circuit; and grounding means for applying the ground potential to the storage gate electrode only in a predetermined period immediately after a start of application of a power supply voltage to the dynamic RAM.

    摘要翻译： 提供在半导体衬底上的动态RAM包括：存储单元，其包括用于存储电荷作为信息的电容器，所述电容器具有在所述动态RAM的正常操作期间施加除了地电势之外的电位的存储栅电极; 包括CMOS电路的外围电路; 以及仅在开始向动态RAM施加电源电压之后的预定时间段内将接地电位施加到存储栅电极的接地装置。