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    Semiconductor device having a nitride barrier for preventing formation of structural defects
    1.
    发明授权
    Semiconductor device having a nitride barrier for preventing formation of structural defects 失效
    具有用于防止形成结构缺陷的氮化物屏障的半导体器件

    公开(公告)号：US06441444B1

    公开(公告)日：2002-08-27

    申请号：US09352401

    申请日：1999-07-14

    申请人： Naoki Tsuji ,  Kiyoteru Kobayashi

    发明人： Naoki Tsuji ,  Kiyoteru Kobayashi

    IPC分类号： H01L2976

    CPC分类号： H01L21/8234 ,  H01L21/76224

    摘要： Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation process after forming the trench isolation structure is controlled thereby making it possible to prevent deterioration of the electrical characteristics of the semiconductor device. A nitriding treatment is applied to the trench surface of the silicon substrate after forming the trench by etching, thereby to form a thin nitride layer having a better effect of preventing oxidation in the interface of silicon.

    摘要翻译： 提供一种制造半导体器件的方法和使用用于隔离半导体元件的沟槽隔离结构的半导体器件的结构，其中控制在形成沟槽隔离结构之后由于氧化处理引起的沟槽填充材料的体积膨胀，从而使得可以 防止半导体器件的电特性劣化。 在通过蚀刻形成沟槽之后，对硅衬底的沟槽表面进行氮化处理，从而形成具有更好的防止硅界面中的氧化的效果的薄氮化物层。

    Non-volatile semiconductor memory device and manufacturing method thereof
    2.
    发明授权
    Non-volatile semiconductor memory device and manufacturing method thereof 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US06469338B2

    公开(公告)日：2002-10-22

    申请号：US09324808

    申请日：1999-06-03

    申请人： Kiyoteru Kobayashi ,  Naoki Tsuji

    发明人： Kiyoteru Kobayashi ,  Naoki Tsuji

    IPC分类号： H01L2994

    CPC分类号： H01L27/11526 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/045 ,  H01L29/7883

    摘要： A non-volatile semiconductor memory device allowing accurate reading of data, having superior charge detection characteristic and high rewriting durability, and free of undesirable writing of a non-selected memory cell transistor is provided. A memory cell transistor 100b includes a silicon substrate 1 having a main surface, a plurality of strip shaped isolating oxide films 4a and 4b formed on the main surface 1b of silicon substrate 1 to continuously extend approximately along the direction, and strip shaped source and drain regions 5b and 6b formed on the main surface 1b of silicon substrate 1 to continuously extend approximately along the direction.

    摘要翻译： 提供了一种非易失性半导体存储器件，其允许具有优异的电荷检测特性和高重写耐久性的数据的精确读取，并且不需要非选择性地写入未选择的存储单元晶体管。 存储单元晶体管100b包括具有主表面的硅衬底1，形成在硅衬底1的主表面1b上的多个带状隔离氧化物膜4a和4b，以沿着<100>方向大致连续延伸，并且带状 源极和漏极区域5b和6b形成在硅衬底1的主表面1b上，以沿着<100>方向大致连续延伸。

    Method of manufacturing semiconductor device
    4.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06756263B2

    公开(公告)日：2004-06-29

    申请号：US10173261

    申请日：2002-06-18

    申请人： Naoki Tsuji

    发明人： Naoki Tsuji

    IPC分类号： H01L2131

    CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/981

    摘要： A semiconductor device includes a trench isolating elements, a memory cell transistor and a peripheral circuit Vcc transistor having a thermal oxide film of a first thickness, and a peripheral circuit Vpp transistor including a thermal oxide film and a thermal oxide film formed before trench formation, having a second thickness greater than the first thickness.

    摘要翻译： 半导体器件包括沟槽隔离元件，存储单元晶体管和具有第一厚度的热氧化膜的外围电路Vcc晶体管，以及包括形成在沟槽形成之前的热氧化物膜和热氧化膜的外围电路Vpp晶体管， 具有大于第一厚度的第二厚度。

    Nonvolatile semiconductor memory device with peripheral circuit part comprising at least one of two transistors having lower conductive layer same perpendicular structure as a floating gate
    5.
    发明授权
    Nonvolatile semiconductor memory device with peripheral circuit part comprising at least one of two transistors having lower conductive layer same perpendicular structure as a floating gate 有权
    具有外围电路部分的非易失性半导体存储器件包括具有与浮置栅极相同垂直结构的较低导电层的两个晶体管中的至少一个晶体管

    公开(公告)号：US06657249B2

    公开(公告)日：2003-12-02

    申请号：US10189575

    申请日：2002-07-08

    申请人： Naho Nishioka ,  Naoki Tsuji

    发明人： Naho Nishioka ,  Naoki Tsuji

    IPC分类号： H01L29788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

    摘要： A nonvolatile semiconductor memory device capable of readily distinctively forming transistors in a peripheral circuit part and a transistor in a memory cell part while minimizing the number of times of high-temperature heat treatment are obtained. In the peripheral circuit part, at least one of a first transistor and a second transistor has a lower conductive layer having the same perpendicular structure as a floating gate, an intermediate insulator film including an insulator film of the same perpendicular structure as an inter-gate isolation film and an upper conductive layer of the same perpendicular structure as a conductive layer of a control gate in ascending order on a gate insulator film thereof, and the intermediate insulator film includes a conduction part electrically connecting the upper conductive layer and the lower conductive layer with each other.

    摘要翻译： 获得能够在最小化高温热处理次数的同时，在外围电路部分中容易地形成晶体管和存储单元部分中的晶体管的非易失性半导体存储器件。 在外围电路部分中，第一晶体管和第二晶体管中的至少一个具有与浮置栅极具有相同垂直结构的下导电层，包括与栅极相同垂直结构的绝缘膜的中间绝缘膜 隔离膜和与导电层相同的垂直结构的上导电层，其栅极绝缘膜上以升序排列，并且中间绝缘膜包括将上导电层和下导电层电连接的导电部分 与彼此。

    Nonvolatile semiconductor device
    6.
    发明授权
    Nonvolatile semiconductor device 有权
    非易失性半导体器件

    公开(公告)号：US06649969B2

    公开(公告)日：2003-11-18

    申请号：US09908895

    申请日：2001-07-20

    申请人： Naoki Tsuji ,  Akinobu Teramoto ,  Kazutoshi Wakao

    发明人： Naoki Tsuji ,  Akinobu Teramoto ,  Kazutoshi Wakao

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： The invention provides a nonvolatile semiconductor device, or the like. According to the fabrication process of the present invention, silica glass containing boron or phosphorous is used as a material of high absorbency, which is treated in the vapor phase HF atmosphere and, therefore, selective etching of silica glass, only, of high absorbency becomes possible so that a void area can be formed beneath the fin of the floating gate. Accordingly, the absolute value of the parasitic capacitance between the floating gate and the substrate is decreased. In addition, the degree of the fluctuation of the parasitic capacitance due to the manufacturing process can be restricted to a low level. Accordingly, a nonvolatile semiconductor device of high performance can be gained without lowering the yield.

    摘要翻译： 本发明提供一种非易失性半导体器件等。 根据本发明的制造方法，使用含有硼或磷的二氧化硅玻璃作为吸收性高的材料，其在气相HF气氛中进行处理，因此，只有具有高吸收性的石英玻璃的选择性蚀刻成为 可能使浮动栅极的鳍下方形成空隙区域。 因此，浮置栅极和衬底之间的寄生电容的绝对值减小。 此外，由于制造过程而引起的寄生电容的波动程度可以被限制在低的水平。 因此，可以获得高性能的非易失性半导体器件而不降低产量。

    Magnetron
    8.
    发明授权
    Magnetron 有权
    磁控管

    公开(公告)号：US06985042B2

    公开(公告)日：2006-01-10

    申请号：US10658411

    申请日：2003-09-10

    申请人： Hideyuki Obata ,  Naoki Tsuji

    发明人： Hideyuki Obata ,  Naoki Tsuji

    IPC分类号： H03B9/10

    CPC分类号： H03B9/10 ,  H01J23/10 ,  H01J25/587

    摘要： The object to the present invention is to provide a magnetron which can reduce spurious oscillation such as the π−1 mode which presents a problem particularly in magnetrons and can reduce spurious radiations without placing filters. The magnetron of the present invention includes an anode 1 formed by plural vanes 12 in such a manner that inner ends 12 are radially extended toward the center of the anode shell 11 from the inner wall of a cylindrical anode shell, and a cathode 2 provided at the center of the anode 1. The magnetron of the present invention further includes a pair of pole pieces 4 provided in such a manner that a magnetic field can be applied on the interaction space 2 where the inner ends 12a of the vanes 12 and the cathode 2 face with each other. At least one of the pair of pole pieces is provided in such a manner that in a range A at least ⅓ of the vane length L from the inner end 12a of the vane, the distance B between the side surfaces 12b of the vanes and the surface 4b adjacent the inner end 4a of the pole pieces 4 is within 0.015 λ wherein λ is the oscillation wavelength of the magnetron, and said vane length is a distance from said one end to said inner end.

    摘要翻译： 本发明的目的是提供一种可以减少诸如pi-1模式的寄生振荡的磁控管，其特别是在磁控管中存在问题，并且可以在不放置过滤器的情况下减少杂散辐射。 本发明的磁控管包括由多个叶片12形成的阳极1，内部端部12从圆柱形阳极壳体的内壁向阳极壳体11的中心径向延伸，阴极2设置在 阳极的中心1。 本发明的磁控管还包括一对磁极片4，其以这样一种方式设置，使得可以将磁场施加在相互作用空间2上，其中叶片12和阴极2的内端部12a相互面对。 一对极片中的至少一个以这样的方式设置，使得在从叶片的内端12a的叶片长度L的至少1/3的范围A中，侧面12b之间的距离B 叶片和邻近极片4的内端4a的表面4b在0.015λ之内，其中λ是磁控管的振荡波长，并且所述叶片长度是从所述一端到所述内端的距离。