公开(公告)号：US06469338B2

公开(公告)日：2002-10-22

申请号：US09324808

申请日：1999-06-03

申请人： Kiyoteru Kobayashi ,  Naoki Tsuji

发明人： Kiyoteru Kobayashi ,  Naoki Tsuji

IPC分类号： H01L2994

CPC分类号： H01L27/11526 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/045 ,  H01L29/7883

摘要： A non-volatile semiconductor memory device allowing accurate reading of data, having superior charge detection characteristic and high rewriting durability, and free of undesirable writing of a non-selected memory cell transistor is provided. A memory cell transistor 100b includes a silicon substrate 1 having a main surface, a plurality of strip shaped isolating oxide films 4a and 4b formed on the main surface 1b of silicon substrate 1 to continuously extend approximately along the direction, and strip shaped source and drain regions 5b and 6b formed on the main surface 1b of silicon substrate 1 to continuously extend approximately along the direction.

摘要翻译： 提供了一种非易失性半导体存储器件，其允许具有优异的电荷检测特性和高重写耐久性的数据的精确读取，并且不需要非选择性地写入未选择的存储单元晶体管。 存储单元晶体管100b包括具有主表面的硅衬底1，形成在硅衬底1的主表面1b上的多个带状隔离氧化物膜4a和4b，以沿着<100>方向大致连续延伸，并且带状 源极和漏极区域5b和6b形成在硅衬底1的主表面1b上，以沿着<100>方向大致连续延伸。

公开(公告)号：US06441444B1

公开(公告)日：2002-08-27

申请号：US09352401

申请日：1999-07-14

申请人： Naoki Tsuji ,  Kiyoteru Kobayashi

发明人： Naoki Tsuji ,  Kiyoteru Kobayashi

IPC分类号： H01L2976

CPC分类号： H01L21/8234 ,  H01L21/76224

摘要： Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation process after forming the trench isolation structure is controlled thereby making it possible to prevent deterioration of the electrical characteristics of the semiconductor device. A nitriding treatment is applied to the trench surface of the silicon substrate after forming the trench by etching, thereby to form a thin nitride layer having a better effect of preventing oxidation in the interface of silicon.

摘要翻译： 提供一种制造半导体器件的方法和使用用于隔离半导体元件的沟槽隔离结构的半导体器件的结构，其中控制在形成沟槽隔离结构之后由于氧化处理引起的沟槽填充材料的体积膨胀，从而使得可以 防止半导体器件的电特性劣化。 在通过蚀刻形成沟槽之后，对硅衬底的沟槽表面进行氮化处理，从而形成具有更好的防止硅界面中的氧化的效果的薄氮化物层。

公开(公告)号：US07517800B2

公开(公告)日：2009-04-14

申请号：US11033739

申请日：2005-01-13

申请人： Tomonori Okudaira ,  Takeshi Hayashi ,  Hiroshi Fujiwara ,  Yasushi Fujita ,  Kiyoteru Kobayashi

发明人： Tomonori Okudaira ,  Takeshi Hayashi ,  Hiroshi Fujiwara ,  Yasushi Fujita ,  Kiyoteru Kobayashi

IPC分类号： H01L21/00

CPC分类号： C23C16/4408 ,  C23C16/34 ,  C23C16/56 ,  H01L21/28088 ,  H01L21/28556 ,  H01L27/10811 ,  H01L27/10894 ,  H01L28/60

摘要： A manufacturing method of a semiconductor device including a TiN film, including a deposition step of forming a TiN film by the CVD method, an anneal step of performing a heat treatment to the formed TiN film in an atmosphere of NH3 gas, an NH3 gas purge step of purging NH3 gas, and a step of further repeating the deposition step, the anneal step, and the NH3 gas purge step for at least one time. The deposition step is performed using titanium halide gas and NH3 gas as material gases and with a deposition temperature of 300° C.-450° C. to form the TiN film by a thickness of 1 nm-5 nm for each deposition step. Thus, a semiconductor device in which generation of irregularly grown objects in the TiN film is suppressed and a manufacturing method thereof can be provided.

摘要翻译： 一种包括TiN膜的半导体器件的制造方法，包括通过CVD法形成TiN膜的沉积步骤，在NH 3气体气氛中对形成的TiN膜进行热处理的退火步骤，NH 3气体吹扫 吹扫NH 3气体的步骤，以及进一步重复沉积步骤，退火步骤和NH 3气体吹扫步骤至少一次的步骤。 沉积步骤使用卤化钛气体和NH 3气体作为原料气体，并且沉积温度为300℃-450℃，以便在每个沉积步骤中形成厚度为1nm-5nm的TiN膜。 因此，可以抑制在TiN膜中产生不规则生长的物体的半导体器件及其制造方法。

公开(公告)号：US5017982A

公开(公告)日：1991-05-21

申请号：US432430

申请日：1989-11-06

申请人： Kiyoteru Kobayashi

发明人： Kiyoteru Kobayashi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/92

CPC分类号： H01L27/10808 ,  H01L28/40

摘要： A capacitor including two electrode layers and a dielectric interposed between the electrode layers. The dielectric layer includes a silicon nitride film and a silicon oxide film formed on the surface of the silicon nitride film. The thickness of the silicon oxide film is not smaller than 25 .ANG. and not larger than 35 .ANG.. In this thickness range there is attained the maximum capacitor life. The capacitor is used in a semiconductor memory, improving the device reliability.

摘要翻译： 电容器包括两个电极层和介于电极层之间的电介质。 电介质层包括形成在氮化硅膜表面上的氮化硅膜和氧化硅膜。 氧化硅膜的厚度不小于25安培，不大于35安培。 在这个厚度范围内达到最大的电容器寿命。 电容器用于半导体存储器，提高了器件的可靠性。

公开(公告)号：US4987092A

公开(公告)日：1991-01-22

申请号：US204581

申请日：1988-06-09

申请人： Kiyoteru Kobayashi ,  Tadashi Nishimura ,  Hiroshi Morita ,  Shuji Nakao ,  Hidekazu Oda ,  Yasuo Inoue

发明人： Kiyoteru Kobayashi ,  Tadashi Nishimura ,  Hiroshi Morita ,  Shuji Nakao ,  Hidekazu Oda ,  Yasuo Inoue

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/11 ,  H01L21/8221 ,  H01L27/1104 ,  H01L27/1108

摘要： An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.

摘要翻译： 公开了一种制造具有堆叠结构的半导体器件的改进方法。 制备p沟道半导体衬底，并且在衬底的主表面上形成n沟道源极和漏极区域以及栅极电极以提供n沟道晶体管。 侧壁由位于n沟道晶体管的栅电极的相对尺寸上的P型单晶硅形成，其中介于侧壁和栅电极之间的绝缘层。 单晶层覆盖了n沟道晶体管的源极，漏极和栅极以及侧壁结构。 存在于侧壁中的P型杂质扩散到单晶层中。

公开(公告)号：US4866493A

公开(公告)日：1989-09-12

申请号：US191762

申请日：1988-05-03

申请人： Hideaki Arima ,  Kiyoteru Kobayashi

发明人： Hideaki Arima ,  Kiyoteru Kobayashi

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A sense transistor of an EEPROM has a conductive diffusion layer which is isolated from the source-drain region of the sense transistor and newly formed on the surface of the semiconductor substrate beneath the floating gate of the sense transistor. The conductive diffusion layer is connected to the control gate of the sense transistor, whereby a capacitance between the control gate and the floating gate is increased without increasing the facing area of the control gate and the floating gate.

摘要翻译： EEPROM的感测晶体管具有导电扩散层，该导电扩散层与感测晶体管的源极 - 漏极区隔离，并且新形成在感测晶体管的浮置栅极之下的半导体衬底的表面上。 导电扩散层连接到感测晶体管的控制栅极，从而增加控制栅极和浮置栅极之间的电容，而不增加控制栅极和浮置栅极的面对面积。

公开(公告)号：US20110092037A1

公开(公告)日：2011-04-21

申请号：US12977573

申请日：2010-12-23

申请人： Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

发明人： Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

IPC分类号： H01L21/336

CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

摘要翻译： 为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中 在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜， 层间绝缘膜。

公开(公告)号：US5500816A

公开(公告)日：1996-03-19

申请号：US203074

申请日：1994-02-28

申请人： Kiyoteru Kobayashi

发明人： Kiyoteru Kobayashi

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A tunnel insulating film is formed on a main surface of a silicon substrate. A floating gate electrode is formed on the tunnel insulating film. A nitride layer formed of a material of the floating gate electrode is formed in the vicinity of an interface between the floating gate electrode and the tunnel insulating film located in a tunnel region A. Therefore, the write/erase characteristics of a non-volatile semiconductor memory device can be improved without decreasing the driving capability of a memory transistor at lower voltages.

摘要翻译： 隧道绝缘膜形成在硅衬底的主表面上。 在隧道绝缘膜上形成浮栅电极。 由位于隧道区域A的浮置栅电极和隧道绝缘膜之间的界面附近形成由浮置栅电极的材料形成的氮化物层。因此，非易失性半导体的写/擦除特性 可以在不降低存储晶体管在较低电压下的驱动能力的情况下改善存储器件。

公开(公告)号：US08084343B2

公开(公告)日：2011-12-27

申请号：US12977573

申请日：2010-12-23

申请人： Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

发明人： Tadashi Yamaguchi ,  Koyu Asai ,  Mahito Sawada ,  Kiyoteru Kobayashi ,  Tatsunori Murata ,  Satoshi Shimizu

IPC分类号： H01L21/20

CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.

摘要翻译： 为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中 在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜， 层间绝缘膜。

公开(公告)号：US20050153573A1

公开(公告)日：2005-07-14

申请号：US11033739

申请日：2005-01-13

申请人： Tomonori Okudaira ,  Takeshi Hayashi ,  Hiroshi Fujiwara ,  Yasushi Fujita ,  Kiyoteru Kobayashi

发明人： Tomonori Okudaira ,  Takeshi Hayashi ,  Hiroshi Fujiwara ,  Yasushi Fujita ,  Kiyoteru Kobayashi

IPC分类号： H01L21/20 ,  C23C16/34 ,  C23C16/44 ,  C23C16/56 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/31 ,  H01L21/469

CPC分类号： C23C16/4408 ,  C23C16/34 ,  C23C16/56 ,  H01L21/28088 ,  H01L21/28556 ,  H01L27/10811 ,  H01L27/10894 ,  H01L28/60

摘要： A manufacturing method of a semiconductor device including a TiN film, including a deposition step of forming a TiN film by the CVD method, an anneal step of performing a heat treatment to the formed TiN film in an atmosphere of NH3 gas, an NH3 gas purge step of purging NH3 gas, and a step of further repeating the deposition step, the anneal step, and the NH3 gas purge step for at least one time. The deposition step is performed using titanium halide gas and NH3 gas as material gases and with a deposition temperature of 300° C.-450° C. to form the TiN film by a thickness of 1 nm-5 nm for each deposition step. Thus, a semiconductor device in which generation of irregularly grown objects in the TiN film is suppressed and a manufacturing method thereof can be provided.

摘要翻译： 一种包括TiN膜的半导体器件的制造方法，包括通过CVD法形成TiN膜的沉积步骤，在NH 3气氛中对形成的TiN膜进行热处理的退火步骤， 吹扫NH 3气体的NH 3气体吹扫步骤，以及进一步重复沉积步骤，退火步骤和NH 3气体的步骤， 3气体吹扫步骤至少一次。 沉积步骤使用卤化钛气体和NH 3气体作为材料气体并且沉积温度为300℃-450℃进行，以形成厚度为1nm的TiN膜， 每个沉积步骤为5nm。 因此，可以抑制在TiN膜中产生不规则生长的物体的半导体器件及其制造方法。