Metal Gate Stack Formation for Replacement Gate Technology
    1.
    发明申请
    Metal Gate Stack Formation for Replacement Gate Technology 有权
    用于替代门技术的金属门堆叠形成

    公开(公告)号:US20120315749A1

    公开(公告)日:2012-12-13

    申请号:US13154578

    申请日:2011-06-07

    IPC分类号: H01L21/336

    摘要: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (Vt) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

    摘要翻译: 通常,本文公开的主题涉及现代复杂的半导体器件及其形成方法,其中可以在基于替换栅极集成制造的HK / MG晶体管元件中实现降低的阈值电压(Vt)。 本文公开的一种说明性方法包括在介电常数约为10或更大的栅介质材料层上形成第一金属栅电极材料层。 该方法还包括将第一金属栅电极材料层暴露于氧扩散过程,在第一金属栅电极材料层上方形成第二金属栅电极材料层,并且至少在第一金属栅电极材料层上调整氧浓度梯度和氮浓度梯度 第一金属栅电极材料层和栅介质材料层。

    Metal gate stack formation for replacement gate technology
    4.
    发明授权
    Metal gate stack formation for replacement gate technology 有权
    用于替代栅极技术的金属栅极叠层形成

    公开(公告)号:US08664103B2

    公开(公告)日:2014-03-04

    申请号:US13154578

    申请日:2011-06-07

    IPC分类号: H01L21/3205

    摘要: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a reduced threshold voltage (Vt) may be achieved in HK/MG transistor elements that are manufactured based on replacement gate electrode integrations. One illustrative method disclosed herein includes forming a first metal gate electrode material layer above a gate dielectric material layer having a dielectric constant of approximately 10 or greater. The method further includes exposing the first metal gate electrode material layer to an oxygen diffusion process, forming a second metal gate electrode material layer above the first metal gate electrode material layer, and adjusting an oxygen concentration gradient and a nitrogen concentration gradient in at least the first metal gate electrode material layer and the gate dielectric material layer.

    摘要翻译: 通常,本文公开的主题涉及现代复杂的半导体器件及其形成方法,其中可以在基于替换栅极集成制造的HK / MG晶体管元件中实现降低的阈值电压(Vt)。 本文公开的一种说明性方法包括在介电常数约为10或更大的栅介质材料层上形成第一金属栅电极材料层。 该方法还包括将第一金属栅电极材料层暴露于氧扩散过程,在第一金属栅电极材料层上形成第二金属栅电极材料层,并且至少在第一金属栅电极材料层上调整氧浓度梯度和氮浓度梯度 第一金属栅电极材料层和栅介质材料层。

    REDUCING EQUIVALENT THICKNESS OF HIGH-K DIELECTRICS IN FIELD EFFECT TRANSISTORS BY PERFORMING A LOW TEMPERATURE ANNEAL
    6.
    发明申请
    REDUCING EQUIVALENT THICKNESS OF HIGH-K DIELECTRICS IN FIELD EFFECT TRANSISTORS BY PERFORMING A LOW TEMPERATURE ANNEAL 审中-公开
    通过执行低温天线降低场效应晶体管中高K电介质的等效厚度

    公开(公告)号:US20120238086A1

    公开(公告)日:2012-09-20

    申请号:US13422221

    申请日:2012-03-16

    IPC分类号: H01L21/28

    摘要: When forming sophisticated high-k metal gate electrode structures, for instance on the basis of a replacement gate approach, superior interface characteristics may be obtained on the basis of using a thermally grown base material, wherein the electrically effective thickness may be reduced on the basis of a low temperature anneal process. Consequently, the superior interface characteristics of a thermally grown base material may be provided without requiring high temperature anneal processes, as are typically applied in conventional strategies using a very thin oxide layer formed on the basis of a wet oxidation chemistry.

    摘要翻译: 当形成复杂的高k金属栅极电极结构时,例如基于替代栅极方法,可以在使用热生长的基材的基础上获得优异的界面特性,其中可以基于 的低温退火工艺。 因此,可以提供热生长的基材的优异的界面特性,而不需要高温退火工艺,如通常在使用基于湿氧化学化学形成的非常薄的氧化物层的常规策略中应用的那样。

    Dry etch polysilicon removal for replacement gates
    9.
    发明授权
    Dry etch polysilicon removal for replacement gates 有权
    用于更换浇口的干蚀刻多晶硅去除

    公开(公告)号:US08673759B2

    公开(公告)日:2014-03-18

    申请号:US13398991

    申请日:2012-02-17

    IPC分类号: H01L21/28

    摘要: Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

    摘要翻译: 半导体器件形成有最后的高K /金属栅极工艺,完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。 实施例包括在基板上形成虚拟栅电极,虚拟栅电极具有氮化物盖,在虚拟栅电极的相对侧上形成隔板,在其间形成栅极沟槽,干蚀刻氮化物盖,使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻,并湿法蚀刻伪栅电极的其余部分。

    DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES
    10.
    发明申请
    DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES 有权
    用于替换盖的干燥多晶硅去除

    公开(公告)号:US20130217221A1

    公开(公告)日:2013-08-22

    申请号:US13398991

    申请日:2012-02-17

    IPC分类号: H01L21/28

    摘要: Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

    摘要翻译: 半导体器件形成有最后的高K /金属栅极工艺,完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。 实施例包括在基板上形成虚拟栅电极,虚拟栅电极具有氮化物盖,在虚拟栅电极的相对侧上形成隔板,在其间形成栅极沟槽,干蚀刻氮化物盖,使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻,并湿法蚀刻伪栅电极的其余部分。