Transmission method and transmission system as well as communications device
    1.
    发明授权
    Transmission method and transmission system as well as communications device 失效
    传输方式和传输系统以及通信设备

    公开(公告)号:US07333518B2

    公开(公告)日:2008-02-19

    申请号:US09883278

    申请日:2001-06-19

    IPC分类号: H04J3/06

    摘要: A transmission method according to the present invention is capable of transmitting and receiving a data signal and information signal among a plurality of devices by full-duplex operation, wherein, when the information signal consecutively repeats a single pattern, a different pattern is inserted between the same patterns before transmission thereof. This minimizes an adverse effect of crosstalk jitter over a transmission line susceptible to crosstalk, and reduces a margin between the transition and sampling point of a signal, thereby suppressing the cost of a CDR circuit.

    摘要翻译: 根据本发明的传输方法能够通过全双工操作在多个设备之间发送和接收数据信号和信息信号,其中当信息信号连续地重复单个模式时,不同的模式插入在 相同的图案在传输之前。 这可以最大限度地减少串扰抖动对易受串扰影响的传输线路的不良影响,并减少信号的转换和采样点之间的余量,从而抑制CDR电路的成本。

    Transmission method and device
    3.
    发明授权
    Transmission method and device 失效
    传输方式和装置

    公开(公告)号:US06980616B1

    公开(公告)日:2005-12-27

    申请号:US09889155

    申请日:2000-01-17

    摘要: A transmission method uses multiple kinds of control codes to be exchanged on a serial transmission path between a sender side and a receiver side, and each of the multiple kinds of control codes has bits smaller in number than a predetermined fixed length. The transmission method includes the steps of inspecting the received bit string in groups of bits of the number of the control code, and thereby determining whether one of the multiple kinds of control codes is present in the serial signal received on the serial transmission path or not, selecting the control code to be sent based on a result of the determination in the determining step, sending, onto the serial transmission path, a bit string containing at least the control code to be sent based on the result of the determination in the determining step, and receiving the data code by inspecting the received bit string in groups of bits of the fixed length in response to the detection of the control code indicating the start of transmission of the data from the opposite side in the determining step.

    摘要翻译: 传输方法使用多种控制码在发送机侧和接收机侧之间的串行传输路径上进行交换,并且多种控制码中的每一种的数目比预定的固定长度小。 发送方法包括以下步骤:以控制码数目的比特组检查接收到的比特串,从而确定在串行传输路径上接收的串行信号中是否存在多种控制码中的一种控制码 基于所述确定步骤中的确定结果来选择要发送的控制代码,基于所述确定中的确定结果,将至少包含要发送的控制代码的比特串发送到所述串行传输路径上 响应于在确定步骤中检测到指示来自相反侧的数据的传输的控制码的检测,通过检查固定长度的比特组的接收的比特串来接收数据代码。

    Picture display apparatus with selectively divided screens, picture display method for selectively dividing screens, and storage medium
    5.
    发明授权
    Picture display apparatus with selectively divided screens, picture display method for selectively dividing screens, and storage medium 有权
    具有选择性分割屏幕的图像显示装置,用于选择性地分割屏幕的图像显示方法和存储介质

    公开(公告)号:US08149335B2

    公开(公告)日:2012-04-03

    申请号:US11878263

    申请日:2007-07-23

    IPC分类号: H04N5/445 H04N5/50 H04N9/74

    摘要: A picture display apparatus, comprising: a synthesizing section for synthesizing divided screens to display a plurality of pictures on a single screen; a menu display section for displaying a menu in which a list of options is displayed, the options enabling a user to select a change to be made to at least one of a number, shapes, relative sizes, and relative positions of the divided screens and types of the pictures, so that the user can select from the options to switch to a corresponding screen arrangement; an icon display section for displaying an icon indicating a border between the divided screens in association with the options; and a border changing section for updating the divided screens according to a change in position of the border, wherein the icon display section displays the icon indicating a result of the change in position of the border before the border changing section updates the divided screens according to the change in position of the border. Thus, the user is informed of what the screen will look like before entering a change of the border.

    摘要翻译: 一种图像显示装置,包括:合成部分,用于合成分割的屏幕以在单个屏幕上显示多个图像; 用于显示其中显示选项列表的菜单的菜单显示部分,使得用户能够选择要对所划分的屏幕的数量,形状,相对尺寸和相对位置中的至少一个进行改变的选项,以及 图像的类型,使得用户可以从选项中选择切换到相应的屏幕布置; 图标显示部分,用于与选项相关联地显示指示划分的屏幕之间的边界的图标; 以及边界改变部分,用于根据边界位置的变化更新划分的屏幕,其中图标显示部分显示在边框改变部分根据边界更改部分更新分割的屏幕之前表示边框位置改变的结果的图标 边界位置的变化。 因此,在进入边界改变之前,向用户通知屏幕将是什么样子。

    IMAGE READING APPARATUS
    6.
    发明申请
    IMAGE READING APPARATUS 有权
    图像阅读器

    公开(公告)号:US20110199655A1

    公开(公告)日:2011-08-18

    申请号:US13029035

    申请日:2011-02-16

    IPC分类号: H04N1/04

    摘要: A image reading apparatus includes a first conveyance unit which is configured to convey a document to a reading position of a platen while pinching the document, a second conveyance unit arranged on a downstream of the platen and configured to convey the document, an upstream rotary member arranged between the first conveyance unit and the second conveyance unit and configured to come into contact with the document at a position on an upstream of the reading position, and a downstream rotary member arranged between the first conveyance unit and the second conveyance unit and configured to come into contact with the document at a position on a downstream of the reading position, wherein a gap between the platen and the upstream rotary member is set smaller than a gap between the platen and the downstream rotary member.

    摘要翻译: 图像读取装置包括:第一输送单元,其被构造成在夹持原稿的同时将原稿输送到压纸盘的读取位置;第二输送单元,布置在压纸板的下游并构造成输送原稿;上游旋转构件 布置在所述第一输送单元和所述第二输送单元之间并构造成在所述读取位置的上游的位置处与所述原稿接触;以及下游旋转构件,布置在所述第一输送单元和所述第二输送单元之间, 在读取位置的下游位置处与文件接触,其中压板和上游旋转构件之间的间隙被设定为小于压板和下游旋转构件之间的间隙。

    WIRELESS RECEIVER
    7.
    发明申请
    WIRELESS RECEIVER 失效
    无线接收器

    公开(公告)号:US20080165862A1

    公开(公告)日:2008-07-10

    申请号:US11775252

    申请日:2007-07-10

    IPC分类号: H04N7/24

    摘要: A bitstream analysis circuit, generates a reference clock control data. A reference clock DPLL receives a system clock signal and reference clock control data from the analysis circuit and generates a reference clock signal. The reference clock DPLL comprises a 1/n frequency dividing circuit for frequency-dividing the system clock signal, and a 1/(n+1) frequency dividing circuit for frequency-dividing the system clock signal. A register stores data to set frequency dividing ratios of both frequency dividing circuits. A mixing ratio set register stores data to set a mixing ratio between output clock signals from both frequency dividing circuits and a mixing circuit, and mixes the output clock signals from both frequency dividing circuits at a mixing ratio in response to the data in the mixing ratio setting register.

    摘要翻译: 比特流分析电路,生成参考时钟控制数据。 参考时钟DPLL从分析电路接收系统时钟信号和参考时钟控制数据,并产生参考时钟信号。 参考时钟DPLL包括用于对系统时钟信号进行分频的1 / n分频电路和用于对系统时钟信号进行分频的1 /(n + 1)分频电路。 寄存器存储数据以设置两个分频电路的分频比。 混合比设定寄存器存储数据,以设定来自两个分频电路和混合电路的输出时钟信号之间的混合比,并且以混合比率混合来自两个分频电路的输出时钟信号,混合比率 设定寄存器。

    Receiving apparatus and transmitting apparatus
    8.
    发明申请
    Receiving apparatus and transmitting apparatus 审中-公开
    接收装置和发送装置

    公开(公告)号:US20060268842A1

    公开(公告)日:2006-11-30

    申请号:US11439196

    申请日:2006-05-24

    IPC分类号: H04L12/66 H04L12/56

    摘要: A communication terminal of the present invention includes: (i) judgment section for whether or not a hidden identifier hidden from the user and assigned fixedly and uniquely to each communication terminal or the like is included in response data transmitted from another communication apparatus in reply to transmission of connection request data including data requesting connection with the communication apparatus; and (ii) response data generating section for generating, in later calls in cases where the hidden identifier is judged to be included in the response data, reply data including (i) the hidden identifier assigned to the communication terminal and (ii) the hidden identifier received from the communication terminal.

    摘要翻译: 本发明的通信终端包括:(i)判断部分,其是否包含在从另一个通信装置发回的响应数据中回复给用户隐藏的隐藏标识符并且固定和唯一地分配给每个通信终端等 连接请求数据的发送,包括请求与通信装置的连接的数据; 以及(ii)响应数据生成部,其用于在所述隐藏标识符被判断为包含在所述响应数据中的情况下,在后续呼叫中生成回复数据,所述应答数据包括:(i)分配给所述通信终端的隐藏标识符,以及(ii) 从通信终端接收的标识符。

    Microprocessor including memory for storing set value used to select and executive instruction after completing exception handling caused by exception request
    10.
    发明授权
    Microprocessor including memory for storing set value used to select and executive instruction after completing exception handling caused by exception request 失效
    微处理器包括用于存储设置值的存储器,用于在完成由异常请求引起的异常处理之后选择和执行指令

    公开(公告)号:US06757810B1

    公开(公告)日:2004-06-29

    申请号:US09657906

    申请日:2000-09-08

    IPC分类号: G06F132

    摘要: A control section sets a value “1” to a first flip-flop when a core executes a halt instruction. An OR circuit halts to output the clock. When the detection section detects an occurrence of the exception request, the control section copies the value “1” of the first flip-flop to a second flip-flop and then sets the value “0” to the first flip-flop to restart the supply of the clock to the core through the circuit. When detecting that the value “1” is set in the second flip-flop, the core judges that the state of the core was in the halt state when the exception request occurred, the core returns to the halt state after the completion of the exception handling by executing the halt instruction. When the second flip-flop does not store the value “1”, the core executes an instruction next to the address of the halt instruction.

    摘要翻译: 当核心执行停止指令时,控制部分向第一触发器设置值“1”。 OR电路停止输出时钟。 当检测部分检测到异常请求的发生时,控制部分将第一触发器的值“1”复制到第二触发器,然后将值“0”设置到第一触发器以重新开始 通过电路将时钟提供给核心。 当检测到第二个触发器中设置了值“1”时,核心在发生异常请求时判断核心的状态处于停止状态,核心在完成异常之后返回到停止状态 通过执行停止指令进行处理。 当第二触发器不存储值“1”时,核心执行停止指令的地址旁边的指令。