公开(公告)号：US20110207275A1

公开(公告)日：2011-08-25

申请号：US13126112

申请日：2010-07-28

申请人： Koutarou Tanaka ,  Masahiko Niwayama ,  Masao Uchida

发明人： Koutarou Tanaka ,  Masahiko Niwayama ,  Masao Uchida

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068

摘要： A method of producing a semiconductor device according to the present invention includes: a step of implanting an impurity into a semiconductor layer 2 by using a first implantation mask layer 30, thereby forming a body region 6; a step of implanting an impurity by using the first implantation mask layer 30 and a second implantation mask layer 31, thereby forming a contact region 7 within the body region 6; a step of forming a third implantation mask layer 32, and thereafter selectively removing the second implantation mask layer 31; a step of forming a side wall 34 on a side face of the first implantation mask layer 30; and a step of implanting an impurity to form a source region 8 within the body region 6.

摘要翻译： 根据本发明的制造半导体器件的方法包括：通过使用第一注入掩模层30将杂质注入半导体层2，从而形成体区6的步骤; 通过使用第一注入掩模层30和第二注入掩模层31注入杂质的步骤，从而在体区6内形成接触区7; 形成第三注入掩模层32的步骤，然后选择性地除去第二注入掩模层31; 在第一注入掩模层30的侧面上形成侧壁34的步骤; 以及植入杂质以在体区6内形成源区8的步骤。

公开(公告)号：US08222107B2

公开(公告)日：2012-07-17

申请号：US13126112

申请日：2010-07-28

申请人： Koutarou Tanaka ,  Masahiko Niwayama ,  Masao Uchida

发明人： Koutarou Tanaka ,  Masahiko Niwayama ,  Masao Uchida

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068

摘要： A method of producing a semiconductor device according to the present invention includes: a step of implanting an impurity into a semiconductor layer 2 by using a first implantation mask layer 30, thereby forming a body region 6; a step of implanting an impurity by using the first implantation mask layer 30 and a second implantation mask layer 31, thereby forming a contact region 7 within the body region 6; a step of forming a third implantation mask layer 32, and thereafter selectively removing the second implantation mask layer 31; a step of forming a side wall 34 on a side face of the first implantation mask layer 30; and a step of implanting an impurity to form a source region 8 within the body region 6.

摘要翻译： 根据本发明的制造半导体器件的方法包括：通过使用第一注入掩模层30将杂质注入半导体层2，从而形成体区6的步骤; 通过使用第一注入掩模层30和第二注入掩模层31注入杂质的步骤，从而在体区6内形成接触区7; 形成第三注入掩模层32的步骤，然后选择性地除去第二注入掩模层31; 在第一注入掩模层30的侧面上形成侧壁34的步骤; 以及植入杂质以在体区6内形成源区8的步骤。

公开(公告)号：US08878194B2

公开(公告)日：2014-11-04

申请号：US14001027

申请日：2012-09-03

申请人： Masahiko Niwayama ,  Masao Uchida

发明人： Masahiko Niwayama ,  Masao Uchida

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L21/04

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/66068 ,  H01L29/7828

摘要： A method for fabricating a semiconductor element according to the present disclosure includes the steps of: (A) forming a first silicon carbide semiconductor layer of a first conductivity type on a semiconductor substrate; (B) forming a first mask to define a body region on the first silicon carbide semiconductor layer; (C) forming a body implanted region of a second conductivity type in the first silicon carbide semiconductor layer using the first mask; (D) forming a sidewall on side surfaces of the first mask; (E) defining a dopant implanted region of the first conductivity type and a first body implanted region of the second conductivity type in the first silicon carbide semiconductor layer using the first mask and the sidewall; and (F) thermally treating the first silicon carbide semiconductor layer.

摘要翻译： 根据本公开的制造半导体元件的方法包括以下步骤：（A）在半导体衬底上形成第一导电类型的第一碳化硅半导体层; （B）形成第一掩模以在第一碳化硅半导体层上限定体区; （C）使用所述第一掩模在所述第一碳化硅半导体层中形成第二导电类型的体注入区域; （D）在第一掩模的侧表面上形成侧壁; （E）使用第一掩模和侧壁在第一碳化硅半导体层中限定第一导电类型的掺杂剂注入区和第二导电类型的第一体注入区; 和（F）对第一碳化硅半导体层进行热处理。

公开(公告)号：US08686439B2

公开(公告)日：2014-04-01

申请号：US13816571

申请日：2012-06-25

申请人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

发明人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7828

摘要： This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

公开(公告)号：US08772788B2

公开(公告)日：2014-07-08

申请号：US14122823

申请日：2012-04-23

申请人： Ryo Ikegami ,  Masao Uchida ,  Yuki Tomita ,  Masahiko Niwayama

发明人： Ryo Ikegami ,  Masao Uchida ,  Yuki Tomita ,  Masahiko Niwayama

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L21/8213 ,  H01L21/823412 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828

摘要： A semiconductor device disclosed in the present application includes: a semiconductor substrate; a first silicon carbide semiconductor layer located on a principal surface of the semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type, and an impurity region of a first conductivity type; a trench provided in the first silicon carbide semiconductor layer so as to reach inside of the drift region; a second silicon carbide semiconductor layer of the first conductivity type located at least on a side surface of the trench so as to be in contact with the impurity region and the drift region; a gate insulating film; a gate electrode; a first ohmic electrode; and a second ohmic electrode. The body region includes a first body region which is in contact with the second silicon carbide semiconductor layer on the side surface of the trench, and a second body region which is in contact with the drift region and has a smaller average impurity concentration than the first body region.

摘要翻译： 本申请中公开的半导体器件包括：半导体衬底; 位于所述半导体衬底的主表面上的第一碳化硅半导体层，所述第一碳化硅半导体层包括第一导电类型的漂移区，第二导电类型的体区和第一导电类型的杂质区 ; 设置在所述第一碳化硅半导体层中以便到达所述漂移区域内部的沟槽; 所述第一导电类型的第二碳化硅半导体层至少位于所述沟槽的侧表面上以与所述杂质区域和所述漂移区域接触; 栅极绝缘膜; 栅电极; 第一欧姆电极; 和第二欧姆电极。 主体区域包括与沟槽侧表面上的第二碳化硅半导体层接触的第一体区域和与漂移区域接触并且具有比第一区域更小的平均杂质浓度的第二体区域 身体区域。

公开(公告)号：US20130140586A1

公开(公告)日：2013-06-06

申请号：US13816571

申请日：2012-06-25

申请人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

发明人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L29/1608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7828

摘要： This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

摘要翻译： 该碳化硅半导体元件包括：位于第一导电类型的漂移层上的第二导电类型的体区; 位于身体区域上的第一导电类型的杂质区域; 穿过身体区域和杂质区域到达漂移层的沟槽; 布置在沟槽表面上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。 沟槽的表面包括与第一侧表面相对的第一侧表面和第二侧表面。 第二导电类型的掺杂剂的浓度至少局部地位于位于第一侧表面旁边的身体区域的部分中，而不是位于第二侧表面旁边的身体区域的另一部分中。

公开(公告)号：US20130328065A1

公开(公告)日：2013-12-12

申请号：US14001027

申请日：2012-09-03

申请人： Masahiko Niwayama ,  Masao Uchida

发明人： Masahiko Niwayama ,  Masao Uchida

IPC分类号： H01L29/16

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/66068 ,  H01L29/7828

摘要： A method for fabricating a semiconductor element according to the present disclosure includes the steps of: (A) forming a first silicon carbide semiconductor layer of a first conductivity type on a semiconductor substrate; (B) forming a first mask to define a body region on the first silicon carbide semiconductor layer; (C) forming a body implanted region of a second conductivity type in the first silicon carbide semiconductor layer using the first mask; (D) forming a sidewall on side surfaces of the first mask; (E) defining a dopant implanted region of the first conductivity type and a first body implanted region of the second conductivity type in the first silicon carbide semiconductor layer using the first mask and the sidewall; and (F) thermally treating the first silicon carbide semiconductor layer.

摘要翻译： 根据本公开的制造半导体元件的方法包括以下步骤：（A）在半导体衬底上形成第一导电类型的第一碳化硅半导体层; （B）形成第一掩模以限定第一碳化硅半导体层上的体区; （C）使用所述第一掩模在所述第一碳化硅半导体层中形成第二导电类型的体注入区域; （D）在第一掩模的侧表面上形成侧壁; （E）使用第一掩模和侧壁在第一碳化硅半导体层中限定第一导电类型的掺杂剂注入区和第二导电类型的第一体注入区; 和（F）对第一碳化硅半导体层进行热处理。

公开(公告)号：US08653535B2

公开(公告)日：2014-02-18

申请号：US13701016

申请日：2011-08-29

申请人： Chiaki Kudou ,  Masahiko Niwayama ,  Ryo Ikegami

发明人： Chiaki Kudou ,  Masahiko Niwayama ,  Ryo Ikegami

IPC分类号： H01L29/15

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7828

摘要： A semiconductor device according to the present invention includes a contact region 201 of a second conductivity type which is provided in a body region 104. The contact region 201 includes a first region 201a in contact with a first ohmic electrode 122 and a second region 201b located at a position deeper than that of the first region 201a and in contact with the body region 104. The first region 201a and the second region 201b each have at least one peak of impurity concentration. The peak of impurity concentration in the first region 201a has a higher value than that of the peak of impurity concentration in the second region 201b.

摘要翻译： 根据本发明的半导体器件包括设置在体区104中的第二导电类型的接触区域201.接触区域201包括与第一欧姆电极122接触的第一区域201a和位于第二区域201b的第二区域201b 在比第一区域201a更深的位置处并且与主体区域104接触。第一区域201a和第二区域201b各自具有至少一个杂质浓度峰。 第一区域201a中的杂质浓度的峰值比第二区域201b中的杂质浓度的峰值高。

公开(公告)号：US07291535B2

公开(公告)日：2007-11-06

申请号：US11000209

申请日：2004-12-01

申请人： Masahiko Niwayama ,  Kenji Yoneda ,  Kazuma Takahashi

发明人： Masahiko Niwayama ,  Kenji Yoneda ,  Kazuma Takahashi

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device includes the steps of: forming a semiconductor region of a first conductive type on a semiconductor wafer; forming a gate electrode on the semiconductor region; on the semiconductor region, forming a first insulating film over the whole surface including the upper surface of the gate electrode; by removing the formed first insulating film through etching from the top surface side, forming first sidewalls, covering the side surfaces of the gate electrode, from the first insulating film; and by implanting first impurity ions of a second conductive type to the semiconductor region by using an ion implantation device capable of processing a plurality of semiconductor wafers collectively, forming first impurity diffusion regions on both sides of the gate electrode in the semiconductor region. In the step of forming the first impurity diffusion regions, implantation of the first impurity ions are dividedly performed a plurality of times, and the semiconductor wafer is rotated in its wafer surface for each ion implantation.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体晶片上形成第一导电类型的半导体区域; 在所述半导体区域上形成栅电极; 在所述半导体区域上，在包括所述栅电极的上表面的整个表面上形成第一绝缘膜; 通过从上表面侧蚀刻去除形成的第一绝缘膜，从第一绝缘膜形成覆盖栅电极的侧表面的第一侧壁; 并且通过使用能够一体地处理多个半导体晶片的离子注入装置将第二导电类型的第一杂质离子注入半导体区域，在半导体区域中的栅电极的两侧形成第一杂质扩散区。 在形成第一杂质扩散区域的步骤中，分散地进行第一杂质离子的注入多次，并且半导体晶片在其晶片表面中进行每次离子注入。

公开(公告)号：US20060163498A1

公开(公告)日：2006-07-27

申请号：US11204050

申请日：2005-08-16

申请人： Kenji Yoneda ,  Masahiko Niwayama

发明人： Kenji Yoneda ,  Masahiko Niwayama

IPC分类号： H01L21/265 ,  H01J37/317

CPC分类号： H01J37/3171 ,  H01J37/3023 ,  H01J2237/0044 ,  H01J2237/043

摘要： Impurity ions are implanted into a semiconductor wafer of which a capacitor insulting film is formed on a principal face. In this impurity ion implantation step, the impurity ions are implanted into the semiconductor wafer in the form of a pulsed beam that repeats ON-OFF operation intermittently.