公开(公告)号：US20090057719A1

公开(公告)日：2009-03-05

申请号：US12180116

申请日：2008-07-25

申请人： Tsuyoshi TAKAHASHI ,  Kozo MAKIYAMA

发明人： Tsuyoshi TAKAHASHI ,  Kozo MAKIYAMA

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/66462 ,  H01L21/02543 ,  H01L21/02587 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/1029 ,  H01L29/42316 ,  H01L29/778 ,  H01L29/7787

摘要： A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.

摘要翻译： 提供了具有台面状元件区域和优异特性的复合半导体器件。 化合物半导体器件具有：InP衬底; 在InP衬底上形成的外延层压台面，并且包括沟道层，沟道层上方的载流子供应层和载体供应层上方的接触顶盖层; 欧姆源电极和漏极形成在盖层上; 通过去除所述源极和漏极之间的所述盖层而形成的凹部，以及使所述载体供给层露出; 绝缘膜，其形成在所述盖层上并且从所述盖层的边缘远离所述凹部缩回; 从所述凹部中的所述载体供给层延伸到所述台面的外部的栅电极; 并且通过将面向栅电极的沟道层的侧部除去在台面外形成的气隙。

公开(公告)号：US20090085063A1

公开(公告)日：2009-04-02

申请号：US12190216

申请日：2008-08-12

申请人： Kozo MAKIYAMA ,  Tsuyoshi TAKAHASHI

发明人： Kozo MAKIYAMA ,  Tsuyoshi TAKAHASHI

IPC分类号： H01L29/267 ,  H01L21/336

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66431

摘要： A method for manufacturing a compound semiconductor device forms an EB resist layer on first SiN film, performs EB exposure at high dose for recess forming opening and at low dose for eaves removing opening, develops the high dose EB resist pattern to etch the first SiN film, selectively etches the cap layer to form a recess wider than the opening of the first SiN film leaving eaves of SiN, develops the low dose EB resist pattern to form the eaves removing opening, etches the first SiN film to extinguish the eaves, forms second SiN film on the exposed surface, forms a resist pattern having a gate electrode opening on the second SiN film to etch the second SiN film, forms a metal layer to form a gate electrode by lift-off. The SiN film in eaves shape will not be left.

摘要翻译： 一种化合物半导体器件的制造方法在第一SiN膜上形成EB抗蚀剂层，以高剂量进行用于凹部形成开口的EB曝光，并以低剂量进行檐部剥离开口的EB曝光，形成高剂量EB抗蚀剂图案以蚀刻第一SiN膜 选择性地蚀刻覆盖层以形成比离开SiN的檐的第一SiN膜的开口更宽的凹陷，形成低剂量EB抗蚀剂图案以形成檐口去除开口，蚀刻第一SiN膜以扑灭檐口，形成第二个 在曝光表面上形成SiN膜，形成在第二SiN膜上具有栅电极开口以蚀刻第二SiN膜的抗蚀剂图案，通过剥离形成金属层以形成栅电极。 檐形状的SiN膜不会留下。

公开(公告)号：US20110053686A1

公开(公告)日：2011-03-03

申请号：US12862017

申请日：2010-08-24

申请人： Tsuyoshi TAKAHASHI ,  Ken MATSUMOTO ,  Kunihiko MORI

发明人： Tsuyoshi TAKAHASHI ,  Ken MATSUMOTO ,  Kunihiko MORI

IPC分类号： A63F9/24

CPC分类号： A63F13/77 ,  A63F13/327 ,  A63F13/34 ,  A63F13/833 ,  A63F2300/402 ,  A63F2300/405 ,  A63F2300/408 ,  A63F2300/5593 ,  A63F2300/8029 ,  H04L67/38

摘要： A game device includes a packet processing section that processes a packet that is transferred between the game device and another game device via a network, a game calculation section that performs a game calculation process based on data transferred using a packet, and an image generation section that generates an image based on a result of the game calculation process. The game calculation section performs a game sequence process as the game calculation process in each game sequence interval. A packet that is transferred between the game device and the other game device includes a packet ID that specifies the type of data transferred using the packet, and an interval ID that specifies the game sequence interval that utilizes data transferred using the packet. The packet processing section compares the interval ID included in a received packet with the interval ID of a current game sequence interval. The game calculation section performs the game calculation process based on data included in a packet when the interval ID included in the packet coincides with the interval ID of the current game sequence interval.

摘要翻译： 一种游戏装置，包括经由网络处理在游戏装置与另一游戏装置之间传送的分组的分组处理部，基于使用分组传送的数据进行游戏计算处理的游戏计算部，以及图像生成部 其基于游戏计算处理的结果生成图像。 游戏计算部分执行游戏顺序处理，作为每个游戏序列间隔中的游戏计算处理。 在游戏装置和其他游戏装置之间传送的分组包括指定使用分组传送的数据的类型的分组ID，以及指定利用使用该分组传送的数据的游戏序列间隔的间隔ID。 分组处理部将接收到的分组中包含的间隔ID与当前游戏序列间隔的间隔ID进行比较。 当包含在包中的间隔ID与当前游戏序列间隔的间隔ID一致时，游戏计算部分执行基于分组中包括的数据的游戏计算处理。

公开(公告)号：US20120043587A1

公开(公告)日：2012-02-23

申请号：US13207761

申请日：2011-08-11

申请人： Tsuyoshi TAKAHASHI

发明人： Tsuyoshi TAKAHASHI

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/205 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/66219 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/861

摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed.

摘要翻译： 半导体器件包括第一导电类型的第一半导体层，与第一半导体层接触形成的第二半导体层和与第二半导体层接触形成的第二导电类型的第三半导体层，第一半导体层 设置有从第一半导体层和第二半导体层之间的界面到给定距离的第一半导体区域，以及第一半导体区域的杂质浓度高于第一半导体区域的杂质浓度以外的第一半导体区域的杂质浓度 形成。

公开(公告)号：US20080272456A1

公开(公告)日：2008-11-06

申请号：US12174010

申请日：2008-07-16

申请人： Tsuyoshi TAKAHASHI

发明人： Tsuyoshi TAKAHASHI

IPC分类号： H01L21/764 ,  H01L23/522

CPC分类号： H01L27/0605 ,  H01L21/743 ,  H01L21/7682 ,  H01L21/8252 ,  H01L23/66 ,  H01L29/0657 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a cavity 46 is formed in the SI-InP substrate 14, the buffer layer 16 and the insulating film below the signal line 52, and pillar-shaped supports in the cavity 46 support the insulating films 34, 36 which are the ceiling of the cavity 46.

摘要翻译： 半导体器件包括在SI-InP衬底14上形成的i-InAlAs层的缓冲层16，形成在缓冲层16上的BCB的绝缘膜24,36，以及包括信号线52和接地线54的共面互连 形成在绝缘膜36上，在SI-InP衬底14，缓冲层16和信号线52下面的绝缘膜上形成空腔46，并且空腔46中的柱状支撑件支撑绝缘膜34,36 这是空腔46的天花板。

公开(公告)号：US20130032856A1

公开(公告)日：2013-02-07

申请号：US13533033

申请日：2012-06-26

申请人： Tsuyoshi TAKAHASHI

发明人： Tsuyoshi TAKAHASHI

IPC分类号： H01L29/267

CPC分类号： H01L29/267 ,  H01L29/66219 ,  H01L29/882

摘要： A semiconductor apparatus includes: a semiconductor apparatus includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a third semiconductor layer of the first conductivity type, wherein: the second semiconductor layer is formed between the first and third semiconductor layers, and the first and second semiconductor layers are in contact with each other; and a first energy level at a bottom edge of a conduction band of the first semiconductor layer is lower than a second energy level at a top edge of a valence band of the second semiconductor layer, and the second energy level at the top edge of the valence band of the second semiconductor layer is substantially the same as a third energy level at a bottom edge of a conduction band of the third semiconductor layer.

摘要翻译： 半导体装置包括：半导体装置，包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层; 以及第一导电类型的第三半导体层，其中：所述第二半导体层形成在所述第一和第三半导体层之间，并且所述第一和第二半导体层彼此接触; 并且在第一半导体层的导带的底部边缘处的第一能级低于第二半导体层的价带的顶边缘处的第二能级，并且第二能级处于第 第二半导体层的价带基本上与第三半导体层的导带的底边缘处的第三能级相同。

公开(公告)号：US20080242113A1

公开(公告)日：2008-10-02

申请号：US12101514

申请日：2008-04-11

申请人： Shintaro AOYAMA ,  Tsuyoshi TAKAHASHI ,  Kouji SHIMOMURA ,  Miki ARUGA

发明人： Shintaro AOYAMA ,  Tsuyoshi TAKAHASHI ,  Kouji SHIMOMURA ,  Miki ARUGA

IPC分类号： H01L21/31

CPC分类号： H01L21/02148 ,  C23C16/0272 ,  C23C16/401 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/02052 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31645 ,  H01L21/318

摘要： A method for forming a high-K dielectric film on a silicon substrate includes the steps of processing a surface of the silicon substrate with a diluted hydrofluoric acid, conducting nucleation process of HfN, after the step of processing with the diluted hydrofluoric acid, by supplying a metal organic source containing Hf and nitrogen to the surface of said silicon substrate, and forming an Hf silicate film by a CVD process, after the step of nucleation, by supplying a metal organic source containing Hf and a metal organic source containing Si to the surface of the silicon substrate.

摘要翻译： 在硅衬底上形成高K电介质膜的方法包括以下步骤：用稀氢氟酸处理硅衬底的表面，在用稀氢氟酸处理步骤之后，通过供给 在所述硅衬底的表面上含有Hf和氮的金属有机源，并且在成核步骤之后通过CVD工艺形成Hf硅酸盐膜，通过将含有Hf的金属有机源和含Si的金属有机源供给到 硅衬底的表面。

公开(公告)号：US20100165694A1

公开(公告)日：2010-07-01

申请号：US12644628

申请日：2009-12-22

申请人： Tsuyoshi TAKAHASHI ,  Shigeo Furuta ,  Yuichiro Masuda ,  Masatoshi Ono

发明人： Tsuyoshi TAKAHASHI ,  Shigeo Furuta ,  Yuichiro Masuda ,  Masatoshi Ono

IPC分类号： G11C5/06 ,  G11C7/00

CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

摘要： Disclosed is a memory cell array including: word lines and first and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and a switching element formed inside a contact hole, the switching element includes first and second conductive layers and a gap in which a resistance value is changed by applying a predetermined voltage, each word line is connected to a gate electrode, each first bit line is connected to a second electrode, each second bit line is connected to the second conductive layer, and data is written by supplying a write voltage to the first bit line connected to the selected memory cell and specifying the word line connected to the memory cell, and data is read by supplying a read voltage to the first bit lines connected to the memory cell and specifying the word line connected to the memory cells.

摘要翻译： 公开了一种存储单元阵列，包括：字线和分别连接到存储单元的第一和第二位线，其中每个存储单元包括MOS晶体管和形成在接触孔内的开关元件，所述开关元件包括第一和第二导电层， 通过施加预定电压来改变电阻值的间隙，每个字线连接到栅电极，每个第一位线连接到第二电极，每个第二位线连接到第二导电层，并且数据 通过向连接到所选择的存储单元的第一位线提供写入电压并指定连接到存储单元的字线来写入写入电压，并且通过向连接到存储器单元的第一位线提供读取电压并指定 字线连接到存储单元。

公开(公告)号：US20090161407A1

公开(公告)日：2009-06-25

申请号：US12338313

申请日：2008-12-18

申请人： Yuichiro MASUDA ,  Shigeo FURUTA ,  Tsuyoshi TAKAHASHI ,  Tetsuo SHIMIZU ,  Yasuhisa NAITOH ,  Masayo HORIKAWA

发明人： Yuichiro MASUDA ,  Shigeo FURUTA ,  Tsuyoshi TAKAHASHI ,  Tetsuo SHIMIZU ,  Yasuhisa NAITOH ,  Masayo HORIKAWA

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/009 ,  Y10S977/708 ,  Y10S977/723 ,  Y10S977/94 ,  Y10S977/943

摘要： A nanogap switching element is equipped with an inter-electrode gap portion including a gap of a nanometer order between a first electrode and a second electrode. A switching phenomenon is caused in the inter-electrode gap portion by applying a voltage between the first and second electrodes. The nanogap switching element is shifted from its low resistance state to its high resistance state by receiving a voltage pulse application of a first voltage value, and shifted from its high resistance state to its low resistance state by receiving a voltage pulse application of a second voltage value lower than the first voltage value. When the nanogap switching element is shifted from the high resistance state to the low resistance state, a voltage pulse of an intermediate voltage value between the first and second voltage values is applied thereto before the voltage pulse application of the second voltage value thereto.

摘要翻译： 纳米点开关元件配备有包括第一电极和第二电极之间的纳米级间隙的电极间间隙部分。 通过在第一和第二电极之间施加电压，在电极间间隙部分产生切换现象。 纳米点开关元件通过接收第一电压值的电压脉冲而从其低电阻状态转移到其高电阻状态，并且通过接收施加第二电压的电压脉冲从其高电阻状态转移到其低电阻状态 值低于第一电压值。 当纳米点开关元件从高电阻状态移动到低电阻状态时，在施加第二电压值的电压脉冲之前，施加第一和第二电压值之间的中间电压值的电压脉冲。