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    Overmold integrated circuit package
    1.
    发明授权
    Overmold integrated circuit package 有权
    封装集成电路封装

    公开(公告)号：US06519844B1

    公开(公告)日：2003-02-18

    申请号：US09940130

    申请日：2001-08-27

    申请人： Kumar Nagarajan ,  Seng Sooi Lim ,  Chok J. Chia

    发明人： Kumar Nagarajan ,  Seng Sooi Lim ,  Chok J. Chia

    IPC分类号： H05K330

    CPC分类号： H01L24/32 ,  H01L23/13 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

    摘要： An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound. Fluid communication between the plurality of vias and the air space may be provided by not tenting the vias with a solder mask layer, or by removing any solder mask or other material which may have filled or tented over the vias during processing of the substrate.

    摘要翻译： 描述了一种集成电路封装制造工艺，其减少或消除了在管芯和下层衬底之间的模塑料中形成空隙。 该方法包括提供在上表面上方具有上表面和空气空间的基底。 导电孔通过衬底的上表面形成，其至少部分延伸通过衬底，并且在通孔和上覆空气空间之间提供流体连通。 该过程包括在集成电路管芯的至少一部分通孔之上附接集成电路管芯到衬底的上表面，同时在管芯和衬底的上表面之间留下间隙。 该方法还包括使模塑料流动到模具和衬底的上表面之间的间隙中，同时保持通孔和空气空间之间的流体连通。 以这种方式，被迫在模塑料和衬底的上表面之间被捕获的空气被迫流入通孔，而不是在模塑料中形成空隙。 多个通孔和空气空间之间的流体连通可以通过不用通孔焊接掩模层来提供，或者通过在衬底的处理期间移除可能已经填充或覆盖过孔的任何焊接掩模或其他材料来提供。

    Process for using a removeable plating bus layer for high density substrates
    3.
    发明授权
    Process for using a removeable plating bus layer for high density substrates 失效
    使用可移除电镀总线层用于高密度基板的工艺

    公开(公告)号：US5981311A

    公开(公告)日：1999-11-09

    申请号：US104838

    申请日：1998-06-25

    申请人： Chok J. Chia ,  Seng Sooi Lim ,  Patrick Variot

    发明人： Chok J. Chia ,  Seng Sooi Lim ,  Patrick Variot

    IPC分类号： H01L21/48 ,  H05K3/24 ,  H05K3/42 ,  H01L21/58 ,  H01L21/28 ,  H01L21/304

    CPC分类号： H05K3/242 ,  H01L21/4846 ,  H05K3/428 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K2203/0191 ,  H05K2203/0361 ,  H05K2203/1572

    摘要： A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating. Electroplating the exposed trace areas on the IC substrate with conductive material (such as gold or nickel) by using the removable plating bus as the electrical connection to the exposed metal traces and removing the removable plating bus after electroplating is finished.

    摘要翻译： 一种使用可移除电镀母线电镀高密度集成电路（IC）衬底的方法，包括以下步骤：提供由其表面上形成有多个导电迹线的非导电材料制成的IC衬底。 将可移除的电镀母线安装到IC基板上，覆盖多个导电迹线。 在预定位置形成通孔（或通孔）。 穿过可移除电镀总线和IC基板的孔，暴露孔中选定导电迹线的边缘。 用诸如铜的导电材料（例如铜）电镀通孔，其将可移除的电镀总线电连接到孔中的迹线的暴露边缘。 用电镀抗蚀剂涂覆IC基板（包括可移除电镀总线），并与电镀抗蚀剂一起选择性地去除可移除电镀母线的部分，以暴露需要电镀的IC基板上的选定区域的痕迹。 通过使用可移除的电镀母线作为与暴露的金属迹线的电气连接，并且在电镀完成之后移除可移除的电镀母线，用导电材料（例如金或镍）电镀IC衬底上的暴露痕迹区域。

    System and method for packaging an integrated circuit using encapsulant injection
    4.
    发明授权
    System and method for packaging an integrated circuit using encapsulant injection 失效
    使用密封剂注射包装集成电路的系统和方法

    公开(公告)号：US6081997A

    公开(公告)日：2000-07-04

    申请号：US911418

    申请日：1997-08-14

    申请人： Chok J. Chia ,  Seng Sooi Lim ,  Maniam Alagaratnam

    发明人： Chok J. Chia ,  Seng Sooi Lim ,  Maniam Alagaratnam

    IPC分类号： H01L21/56 ,  H05K3/30

    CPC分类号： H01L21/565 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18161 ,  Y10T29/49121 ,  Y10T29/49144 ,  Y10T29/49146

    摘要： A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant. The liquid encapsulant is preferably a C4 underfill material. By injecting the liquid encapsulant under pressure, the amount of time required to dispense the liquid encapsulant is reduced as well as the number of voids present in the liquid encapsulant. Following at least partial curing of the encapsulant, the mold sections are separated, and the packaged semiconductor device is removed. When fully cured and hardened, the encapsulant adheres to the adjacent surfaces of the integrated circuit and the substrate, essentially interlocking the surfaces.

    摘要翻译： 提出了一种用于在集成电路周围形成网格阵列器件封装的系统和方法。 集成电路包括在下表面上的多个I / O焊盘，并且衬底的上表面包括相应的一组焊盘。 衬底还具有延伸穿过其中并且优选地基本上在该组焊盘的中心的开口（即，孔）。 形成在集成电路的I / O焊盘上的焊料凸块被放置成与该组接合焊盘的相应部件直接接触，然后被加热直到它们以C4连接方式流动。 在I / O和接合焊盘的C4连接之后，衬底和附接的集成电路位于形成在两个模具部分之间的模具腔内，并且通过衬底的开口注入液体密封剂材料，使得密封剂填充 模腔。 耦合的I / O和接合焊盘被液体密封剂包围。 液体密封剂优选为C4底部填充材料。 通过在压力下注入液体密封剂，减少了分配液体密封剂所需的时间以及存在于液体密封剂中的空隙数。 在密封剂至少部分固化之后，分离模具部分，并且去除封装的半导体器件。 当完全固化和硬化时，密封剂粘附到集成电路和基板的相邻表面，基本上使表面互锁。