公开(公告)号：US06738499B1

公开(公告)日：2004-05-18

申请号：US09830574

申请日：2001-07-02

申请人： Kunio Doi ,  Katsumi Nakamura

发明人： Kunio Doi ,  Katsumi Nakamura

IPC分类号： G06K900

CPC分类号： G06T7/0012 ,  G06T2207/30061

摘要： A method, computer program product, and system (100) for computerized analysis of the likelihood of malignancy in a pulmonary nodule using artificial neural networks (ANNs) (S4). The method, on which the computer program product and the system is based on, includes obtaining a digital outline of a nodule; generating objective measures corresponding to physical features of the outline of the nodule; applying the generated objective measures to an ANN; and determining a likelihood of malignancy of the nodule based on an output of the ANN. Techniques include novel developments and implementations of artificial neural networks and feature extraction for digital images. Output from the inventive method yields an estimate of the likelihood of malignancy (S7) for a pulmonary nodule.

摘要翻译： 一种用于使用人造神经网络（ANN）对肺结节恶性肿瘤的可能性进行计算机化分析的方法，计算机程序产品和系统（100）（S4）。 计算机程序产品和系统所基于的方法包括获得结节的数字轮廓; 产生对应于结节轮廓的物理特征的客观测量; 将生成的客观措施应用于ANN; 以及基于所述ANN的输出确定所述结节恶性的可能性。 技术包括人造神经网络的新颖开发和实现以及数字图像的特征提取。 本发明方法的输出产生肺结节的恶性可能性（S7）的估计。

公开(公告)号：US09287391B2

公开(公告)日：2016-03-15

申请号：US14370048

申请日：2012-03-05

申请人： Ze Chen ,  Katsumi Nakamura

发明人： Ze Chen ,  Katsumi Nakamura

IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L29/423 ,  H01L29/40

CPC分类号： H01L29/0634 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/4236 ,  H01L29/7397

摘要： A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm.

摘要翻译： 半导体器件包括其中限定有源区和边缘终端区的半导体衬底，形成在有源区中的半导体元件，以及形成在从有源区的边缘部分到 边缘端接区域。 第一至第四P层分别具有按此顺序降低的表面浓度P（1）至P（4），以该顺序增加的底端距离D（1）至D（4），距离B（1） 到B（4）到依次增加的半导体衬底的边缘。 表面浓度P（4）是半导体衬底的杂质浓度的10〜1000倍，底端距离D（4）在15〜30μm的范围内。

公开(公告)号：US08698195B2

公开(公告)日：2014-04-15

申请号：US13329727

申请日：2011-12-19

申请人： Daisuke Oya ,  Katsumi Nakamura

发明人： Daisuke Oya ,  Katsumi Nakamura

IPC分类号： H01L29/66

CPC分类号： H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4236

摘要： A stabilizing plate portion is formed in a region of a first main surface lying between first and second insulated gate field effect transistor portions. The stabilizing plate portion includes a first stabilizing plate arranged closest to the first insulated gate field effect transistor portion and a second stabilizing plate arranged closest to the second insulated gate field effect transistor portion. An emitter electrode is electrically connected to an emitter region of each of the first and second insulated gate field effect transistor portions, electrically connected to each of the first and second stabilizing plates, and arranged on the entire first main surface lying between the first and second stabilizing plates, with an insulating layer being interposed.

摘要翻译： 在位于第一和第二绝缘栅场效应晶体管部分之间的第一主表面的区域中形成稳定板部分。 稳定板部分包括最靠近第一绝缘栅场效应晶体管部分布置的第一稳定板和最靠近第二绝缘栅场效应晶体管部分布置的第二稳定板。 发射电极电连接到第一和第二绝缘栅场效应晶体管部分的每个的发射极区域，电连接到第一和第二稳定板中的每一个，并且布置在位于第一和第二绝缘栅极效应晶体管的第一和第二绝缘栅极 稳定板，绝缘层被插入。

公开(公告)号：US07910987B2

公开(公告)日：2011-03-22

申请号：US11267514

申请日：2005-11-07

申请人： Katsumi Nakamura

发明人： Katsumi Nakamura

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

摘要： A gate electrode is provided to fill up a trench while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode located upward beyond a P-type base layer and an N+-type emitter diffusion layer , WT represents the diameter (sectional width) of an inner wall of a linearly extending portion of the trench and WC represents the distance between the boundary (the inner wall of the trench 300) between a gate oxide film and the P-type base layer and an end surface of the gate electrode located upward beyond the trench in a section of the trench , relation of either WG≧1.3·WT or WC≧0.2 μm holds between these dimensions.

摘要翻译： 提供栅极电极13，以填充沟槽300，同时覆盖其开口。 假设WG表示位于P型基极层4和N +型发射极扩散层51之上的栅极电极<13>的头部的直径（截面宽度），WT表示直径（ 沟槽<300>的直线延伸部分的内壁和WC表示栅极氧化膜<11>与P型基极层之间的距离（沟槽300的内壁）之间的距离 在沟槽<300>的部分中位于上方超过沟槽<300>的栅极电极<13>的端面，在这些尺寸之间保持WG≥3.3·WT或WC≥0.2μm的关系。

公开(公告)号：US06897493B2

公开(公告)日：2005-05-24

申请号：US10457658

申请日：2003-06-10

申请人： Tetsuo Takahashi ,  Katsumi Nakamura ,  Tadaharu Minato ,  Masana Harada

发明人： Tetsuo Takahashi ,  Katsumi Nakamura ,  Tadaharu Minato ,  Masana Harada

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/74 ,  H01L29/76 ,  H01L29/768 ,  H01L29/861 ,  H01L29/868 ,  H01L31/111

CPC分类号： H01L29/7397 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/861 ,  H01L29/868

摘要： A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

摘要翻译： pin二极管由p + +集电极区，n型缓冲区，n + SUP区和n + + SUP阴极区形成。 从n + +阴极区域的表面形成沟槽，以通过n + + + / - >阴极区域形成沟槽，以达到n + - SUP区域。 绝缘膜沿沟槽的内壁表面形成。 形成与绝缘膜插入的n + +阴极区的侧壁相对的栅极电极层。 阴极电极形成为与n + +阴极区电连接。 阳极电极形成为与p + +集电极区域电连接。 阴极区域整体形成在彼此平行延伸的沟槽之间的表面上。 因此，可以获得其中简化了栅极控制电路并且具有良好的性能的功率半导体器件。

公开(公告)号：US06710401B2

公开(公告)日：2004-03-23

申请号：US09569031

申请日：2000-05-11

申请人： Katsumi Nakamura ,  Tadaharu Minato ,  Shuuichi Tominaga ,  Katsuomi Shiozawa

发明人： Katsumi Nakamura ,  Tadaharu Minato ,  Shuuichi Tominaga ,  Katsuomi Shiozawa

IPC分类号： H01L2976

CPC分类号： H01L29/7824 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/76286 ,  H01L21/763 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/66378 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7801 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device which includes a substrate made of a semiconductor having a main surface. A trench is selectively formed in the substrate at a predetermined depth from the main surface. An insulating film is formed at an inner wall of the trench. A control electrode layer fills an inside of the trench through the insulating film. An insulating layer protrudes from the main surface on the control electrode layer. At least one of an edge of an opening of the trench and a bottom of the trench has a rounded surface.

摘要翻译： 一种半导体器件，包括由具有主表面的半导体制成的衬底。 在距离主表面的预定深度处，在衬底中选择性地形成沟槽。 绝缘膜形成在沟槽的内壁处。 控制电极层通过绝缘膜填充沟槽的内部。 绝缘层从控制电极层上的主表面突出。 沟槽的开口的边缘和沟槽的底部中的至少一个具有圆形表面。

公开(公告)号：US06218217B1

公开(公告)日：2001-04-17

申请号：US09618761

申请日：2000-07-18

申请人： Akio Uenishi ,  Katsumi Nakamura

发明人： Akio Uenishi ,  Katsumi Nakamura

IPC分类号： H01L2974

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/7397

摘要： In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

摘要翻译： 在具有高击穿电压的半导体器件中，绝缘层被掩埋在位于以预定间距排列的栅极沟槽之间的n-硅衬底中的区域。 该结构增加了发射极附近部分的载流子密度，提高了具有高击穿电压的栅沟槽型IGBT的特性。

公开(公告)号：US06199622B1

公开(公告)日：2001-03-13

申请号：US09362962

申请日：1999-07-30

申请人： Katsuji Mashio ,  Fumihiro Inoue ,  Yukinobu Take ,  Hiroshi Koizumi ,  Katsumi Nakamura ,  Hironori Muramoto

发明人： Katsuji Mashio ,  Fumihiro Inoue ,  Yukinobu Take ,  Hiroshi Koizumi ,  Katsumi Nakamura ,  Hironori Muramoto

IPC分类号： F28F900

CPC分类号： F28F9/002 ,  B60K11/04 ,  F28D1/0435 ,  F28D2021/0084 ,  F28D2021/0094 ,  F28F2240/00

摘要： A connecting structure for connecting a radiator having a reinforcement member and a condenser having a bracket is provided. The structure includes a connecting member having a spacer portion and a holding portion integrally formed on opposite sides of a notch. The spacer portion is fittingly inserted into the reinforcement member, and a folded portion of the reinforcement member and the condenser bracket are inserted into the notch. A bolt is inserted through the reinforcement member, the spacer portion, the bracket and the holding portion and a nut is screwed onto a tip of the bolt for clamping the radiator and the condenser together.

摘要翻译： 提供了一种用于连接具有加强构件的散热器和具有托架的冷凝器的连接结构。 该结构包括具有间隔部分和一体地形成在凹口的相对侧上的保持部分的连接部件。 间隔部分适配地插入到加强件中，并且加强件和冷凝器支架的折叠部分插入槽口中。 螺栓穿过加强构件，间隔件部分，支架和保持部分，螺母被拧在螺栓的顶端上，用于将散热器和冷凝器夹紧在一起。

公开(公告)号：US06173766B1

公开(公告)日：2001-01-16

申请号：US09013221

申请日：1998-01-26

申请人： Katsumi Nakamura ,  Michitake Sumida

发明人： Katsumi Nakamura ,  Michitake Sumida

IPC分类号： F28B706

CPC分类号： F28D1/05375 ,  F28D1/0435 ,  F28D2021/0084 ,  F28D2021/0094 ,  F28F9/0212 ,  F28F2009/0287 ,  F28F2215/02

摘要： An integrated heat exchanger includes a radiator having a core formed between a pair of radiator tanks, a condenser adjoining the radiator and having the core formed between a pair of condenser tanks, and a corrugated fin provided in the core and shared between the radiator and the condenser, the heat exchanger containing first partitions which divide the inside of the pair of condenser tanks to thereby create fluid chambers on one side of the respective condenser tanks in such a way as to become opposite to each other; and a fluid inflow pipe and a fluid outflow pipe connected to the fluid chamber of the condenser tanks.

摘要翻译： 集成热交换器包括散热器，散热器具有形成在一对散热器箱之间的芯体，邻接散热器的冷凝器和形成在一对冷凝器容器之间的芯体，以及设置在芯体中并在散热器和 冷凝器，所述热交换器包含分隔所述一对冷凝器罐的内部的第一隔板，从而在相应的冷凝器箱的一侧上以彼此相反的方式产生流体室; 以及连接到冷凝罐的流体室的流体流入管和流体流出管。

公开(公告)号：US6111290A

公开(公告)日：2000-08-29

申请号：US178767

申请日：1998-10-26

申请人： Akio Uenishi ,  Katsumi Nakamura

发明人： Akio Uenishi ,  Katsumi Nakamura

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/745

CPC分类号： H01L29/402 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7813

摘要： In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.- silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

摘要翻译： 在具有高击穿电压的半导体器件中，绝缘层被掩埋在位于以预定间距排列的栅极沟槽之间的n-硅衬底中的区域。 该结构增加了发射极附近部分的载流子密度，提高了具有高击穿电压的栅沟槽型IGBT的特性。