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    Dual poly layer and method of manufacture
    2.
    发明授权
    Dual poly layer and method of manufacture 有权
    双层多层及其制造方法

    公开(公告)号：US07208369B2

    公开(公告)日：2007-04-24

    申请号：US10662609

    申请日：2003-09-15

    申请人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

    发明人： Chih-Yang Pai ,  Min-Hsiung Chiang ,  Chen-Jong Wang ,  Shou-Gwo Wuu

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  Y10S257/903 ,  Y10S257/904

    摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.

    摘要翻译： 提供了具有双重多晶硅电极的半导体器件和制造方法。 半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。 每个多晶硅层可以单独掺杂。 该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。 在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

    Integrating a DRAM with an SRAM having butted contacts and resulting devices
    3.
    发明申请
    Integrating a DRAM with an SRAM having butted contacts and resulting devices 审中-公开
    将DRAM与具有对接触点和所产生的器件的SRAM集成

    公开(公告)号：US20080116496A1

    公开(公告)日：2008-05-22

    申请号：US11809642

    申请日：2007-06-01

    申请人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

    发明人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

    IPC分类号： H01L27/108

    CPC分类号： H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116

    摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.

    摘要翻译： 提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。 金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。 形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。 顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。 形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

    1T MIM memory for embedded RAM application in soc
    4.
    发明授权
    1T MIM memory for embedded RAM application in soc 有权
    1T MIM存储器，用于soc中的嵌入式RAM应用

    公开(公告)号：US09012967B2

    公开(公告)日：2015-04-21

    申请号：US13369894

    申请日：2012-02-09

    申请人： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

    发明人： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

    IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L27/02

    CPC分类号： H01L27/10897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894

    摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

    摘要翻译： 嵌入式记忆 这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。 衬底包括晶体管。 第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。 包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。 电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口 层。 顶板开口暴露第二电介质层，并且顶板由电容器共享。

    1T MIM MEMORY FOR EMBEDDED RAM APPLICATION IN SOC
    5.
    发明申请
    1T MIM MEMORY FOR EMBEDDED RAM APPLICATION IN SOC 审中-公开
    1T MIM存储器嵌入式RAM应用于SOC

    公开(公告)号：US20120139022A1

    公开(公告)日：2012-06-07

    申请号：US13369894

    申请日：2012-02-09

    申请人： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

    发明人： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

    IPC分类号： H01L29/92 ,  H01L27/108

    CPC分类号： H01L27/10897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894

    摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

    摘要翻译： 嵌入式记忆 这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。 衬底包括晶体管。 第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。 包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。 电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口 层。 顶板开口暴露第二电介质层，并且顶板由电容器共享。

    MIM capacitor structure and method of manufacture
    6.
    发明申请
    MIM capacitor structure and method of manufacture 有权
    MIM电容器结构及制造方法

    公开(公告)号：US20050082586A1

    公开(公告)日：2005-04-21

    申请号：US10689294

    申请日：2003-10-20

    申请人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Shou-Gwo Wuu ,  Chen-Jong Wang

    发明人： Kuo-Chi Tu ,  Chun-Yao Chen ,  Shou-Gwo Wuu ,  Chen-Jong Wang

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L21/20

    CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

    摘要： A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.

    摘要翻译： 金属绝缘体金属（MIM）电容器结构及其制造方法。 多个MIM电容器图案形成在两个或更多个绝缘层中。 绝缘层可以包括半导体器件的通孔层和金属化层。 顶部绝缘层的顶部凹陷在至少两个相邻的MIM电容器图案之间的区域中。 当MIM电容器的顶板材料沉积时，顶板材料填充相邻MIM电容器图案之间的顶部绝缘层的凹陷区域，形成将相邻的MIM电容器的顶板耦合在一起的连接区域。 MIM电容器底部电极的一部分可以形成在半导体器件的第一金属化层中。

    Three dimensional polysilicon resistor for integrated circuits
    7.
    发明授权
    Three dimensional polysilicon resistor for integrated circuits 失效
    用于集成电路的三维多晶硅电阻器

    公开(公告)号：US5867087A

    公开(公告)日：1999-02-02

    申请号：US791119

    申请日：1997-01-30

    申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chen-Jong Wang ,  Chung-Hui Su

    发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chen-Jong Wang ,  Chung-Hui Su

    IPC分类号： H01L21/02 ,  H01C1/012

    CPC分类号： H01L28/20 ,  Y10T29/49082 ,  Y10T29/49099

    摘要： A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).

    摘要翻译： 一种三维多晶硅电阻器和制造三维多晶硅电阻器的方法。 半导体衬底在其表面上形成绝缘层。 绝缘层具有至少部分地通过绝缘层形成的至少一个孔。 在绝缘层上形成多晶硅层，并保形地形成绝缘层内的孔。 然后对多晶硅层进行构图以形成电阻器，该电阻器包括驻留在孔内的多晶硅层的部分。

    Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance
    9.
    发明授权
    Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance 失效
    用于制造具有低欧姆电阻的薄多晶硅层接触结构的缩小面积金属接触的方法

    公开(公告)号：US5534451A

    公开(公告)日：1996-07-09

    申请号：US429728

    申请日：1995-04-27

    申请人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

    发明人： Shou-Gwo Wuu ,  Mong-Song Liang ,  Chung-Hui Su ,  Chen-Jong Wang

    IPC分类号： H01L21/285 ,  H01L23/485 ,  H01L27/11 ,  H01L29/45 ,  H01L21/283 ,  H01L21/335

    CPC分类号： H01L27/1108 ,  H01L21/28512 ,  H01L23/485 ,  H01L29/458 ,  H01L2924/0002 ,  Y10S257/903

    摘要： A method for fabricating reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The method involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The method provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The method further allows large latitude in etching the contact opening and thereby provides a very manufacturable process.

    摘要翻译： 实现了将薄区域金属触点制造成具有低欧姆电阻的薄多晶硅层接触结构的方法。 该方法包括在由厚多晶硅层构成的缓冲层上形成绝缘层中的接触开口。 开口中的侧壁的一部分包括形成半导体器件的一部分并且还形成与金属接触件的电连接的图案化的多晶硅层。 该方法提供具有非常低的电阻和减小的面积的金属接触以增加器件封装密度。 金属接触结构也消除了形成通常与P + / N +堆叠接触相关联的P + / N +非欧姆结的问题。 该方法进一步允许蚀刻接触开口的大的纬度，从而提供非常可制造的工艺。