公开(公告)号：US07081390B2

公开(公告)日：2006-07-25

申请号：US10614189

申请日：2003-07-08

申请人： Kwan Yong Lim ,  Heung Jae Cho ,  Jung Ho Lee

发明人： Kwan Yong Lim ,  Heung Jae Cho ,  Jung Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66651 ,  H01L21/28123

摘要： Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.

摘要翻译： 公开了半导体器件及其制造方法。 使用具有与氮化物或氧化物不同的蚀刻选择比的材料并且在氧化物栅极预清洁工艺中不被蚀刻的材料在器件隔离膜的顶角形成防蚀刻膜。 因此，可以防止在器件隔离膜和栅极氧化膜的顶角形成护城河，从而提高器件的可靠性和电气特性。

公开(公告)号：US07271066B2

公开(公告)日：2007-09-18

申请号：US11086286

申请日：2005-03-23

申请人： Kwan Yong Lim ,  Heung Jae Cho ,  Jung Ho Lee

发明人： Kwan Yong Lim ,  Heung Jae Cho ,  Jung Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66651 ,  H01L21/28123

摘要： Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.

摘要翻译： 公开了半导体器件及其制造方法。 使用具有与氮化物或氧化物不同的蚀刻选择比的材料并且在氧化物栅极预清洁工艺中不被蚀刻的材料在器件隔离膜的顶角形成防蚀刻膜。 因此，可以防止在器件隔离膜和栅极氧化膜的顶角形成护城河，从而提高器件的可靠性和电气特性。

公开(公告)号：US06828185B2

公开(公告)日：2004-12-07

申请号：US10230345

申请日：2002-08-29

申请人： Kwan Yong Lim ,  Heung Jae Cho ,  Dae Gyu Park ,  In Seok Yeo

发明人： Kwan Yong Lim ,  Heung Jae Cho ,  Dae Gyu Park ,  In Seok Yeo

IPC分类号： H01L218238

CPC分类号： H01L21/823857

摘要： The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.9V of threshold voltage, back bias does not have to be applied separately to achieve the +0.9V threshold voltage, and the device with low power consumption is formed successfully.

摘要翻译： 本发明公开了根据本发明的制造方法制造的具有表面通道的单栅极CMOS通过在栅极氧化物上进行去耦等离子体氮化（DPN）工艺来改善器件的特性，产量和可靠性是非常有利的 电池NMOS和外围PMOS的膜，从而在栅极氧化膜的表面上形成氮化硅。 此外，即使当使用n +多晶硅层的栅电极时，也可以通过整体的简化处理更容易地形成具有表面通道的单栅极CMOS，而不需要单独的瞬态离子注入工艺， 单元NMOS的阈值电压约为+ 0.9V，外围PMOS的阈值电压约为-0.5V及以上，并且外围NMOS的阈值电压约为+ 0.5V及以下。 另外，由于单元NMOS已经具有阈值电压的+ 0.9V，所以不必单独施加反向偏置以实现+ 0.9V阈值电压，并且成功地形成具有低功耗的器件。

公开(公告)号：US06506676B2

公开(公告)日：2003-01-14

申请号：US10033509

申请日：2001-12-27

申请人： Dae Gyu Park ,  Tae Ho Cha ,  Se Aug Jang ,  Heung Jae Cho ,  Tae Kyun Kim ,  Kwan Yong Lim ,  In Seok Yeo ,  Jin Won Park

发明人： Dae Gyu Park ,  Tae Ho Cha ,  Se Aug Jang ,  Heung Jae Cho ,  Tae Kyun Kim ,  Kwan Yong Lim ,  In Seok Yeo ,  Jin Won Park

IPC分类号： H01L2144

CPC分类号： H01L21/28194 ,  C23C14/048 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

摘要： A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

摘要翻译： 制造半导体器件的方法在制造金属栅极的过程中形成表面沟道CMOSFET。 该方法在nMOS区域的栅极绝缘膜上形成具有约4.2至约4.3eV的功函数值的（TixAly）1-zNz膜（其中z范围为约0.0至约0.2），（TixAly）1 -zNz膜（其中z范围为约0.3至约0.6），在pMOS区域中的栅极绝缘膜上具有约4.8至约5.0eV的功函数值，从而在nMOS区域和 pMOS区域。 因此，阈值电压降低。

公开(公告)号：US07157359B2

公开(公告)日：2007-01-02

申请号：US10036156

申请日：2001-12-26

申请人： Dae Gyu Park ,  Heung Jae Cho ,  Kwan Yong Lim

发明人： Dae Gyu Park ,  Heung Jae Cho ,  Kwan Yong Lim

IPC分类号： H01L21/3205

CPC分类号： H01L29/4966 ,  H01L21/28088

摘要： A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.

摘要翻译： 一种用于形成金属栅极的方法，其能够防止在形成金属栅极时栅极绝缘膜的特性劣化。 形成金属栅极的方法包括以下步骤：提供具有用于限定有源区的沟槽形状的器件隔离膜的硅衬底; 通过热氧化工艺在硅衬底的表面上形成栅极绝缘膜; 在栅极绝缘膜上依次形成阻挡金属膜和栅极用金属膜; 并且对栅极金属膜，阻挡金属膜和栅极绝缘膜进行图案化，其中通过原子层沉积（ALD）工艺或远程等离子体化学技术进行用于栅极的阻挡金属膜和金属膜的沉积 气相沉积（CVD）工艺。

公开(公告)号：US06987056B2

公开(公告)日：2006-01-17

申请号：US10615478

申请日：2003-07-08

申请人： Kwan Yong Lim ,  Heung Jae Cho ,  Tae Hang Ahn

发明人： Kwan Yong Lim ,  Heung Jae Cho ,  Tae Hang Ahn

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/02318 ,  H01L21/02183 ,  H01L21/02238 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/31658 ,  H01L21/31662 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477

摘要： Disclosed is the method of forming the gate in the semiconductor device. The present method can prevent abnormal oxidization and lifting at the interface of the stack gate consisting of polysilicon and a metal and can be applied to even the single metal gate, by replacing a re-oxidization process for recovering damage of the gate oxide film generated in the gate patterning process with the oxygen plasma treatment.

摘要翻译： 公开了在半导体器件中形成栅极的方法。 本方法可以防止在由多晶硅和金属构成的堆叠栅极的界面处的异常氧化和提升，并且可以应用于甚至单个金属栅极，通过替换用于恢复在...中产生的栅极氧化膜的损伤的再氧化过程 采用氧等离子体处理的栅极图案化工艺。

公开(公告)号：US08288819B2

公开(公告)日：2012-10-16

申请号：US12953255

申请日：2010-11-23

申请人： Yong Soo Kim ,  Hong Seon Yang ,  Se Aug Jang ,  Seung Ho Pyi ,  Kwon Hong ,  Heung Jae Cho ,  Kwan Yong Lim ,  Min Gyu Sung ,  Seung Ryong Lee ,  Tae Yoon Kim

发明人： Yong Soo Kim ,  Hong Seon Yang ,  Se Aug Jang ,  Seung Ho Pyi ,  Kwon Hong ,  Heung Jae Cho ,  Kwan Yong Lim ,  Min Gyu Sung ,  Seung Ryong Lee ,  Tae Yoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L27/10876 ,  H01L29/518 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

摘要翻译： 一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。 栅极导电层填充灯泡型凹陷区域。 栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

公开(公告)号：US06768179B2

公开(公告)日：2004-07-27

申请号：US10663910

申请日：2003-09-17

申请人： Heung Jae Cho ,  Dae Gyu Park ,  Kwan Yong Lim

发明人： Heung Jae Cho ,  Dae Gyu Park ,  Kwan Yong Lim

IPC分类号： H01L2994

CPC分类号： H01L21/823842

摘要： CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below. Meantime, since the cell NMOS has the threshold voltage of +1V thanks to the first metal layer, no separate back bias is necessary, thereby forming a device with low power consumption, which consequently improves characteristics, yield and reliability of the device.

公开(公告)号：US06642132B2

公开(公告)日：2003-11-04

申请号：US10253779

申请日：2002-09-25

申请人： Heung Jae Cho ,  Dae Gyu Park ,  Kwan Yong Lim

发明人： Heung Jae Cho ,  Dae Gyu Park ,  Kwan Yong Lim

IPC分类号： H01L213205

CPC分类号： H01L21/823842

摘要： CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region −0.5V and below, and the threshold voltage of the peripheral circuit region NMOS +0.5V and below. Meantime, since the cell NMOS has the threshold voltage of +1V thanks to the first metal layer, no separate back bias is necessary, thereby forming a device with low power consumption, which consequently improves characteristics, yield and reliability of the device.

摘要翻译： CMOS器件布置具有表面沟道，以及通过在单元区域NMOS上形成具有4.8至5.0eV的功函数的第一金属层，多晶硅层和第二金属层的多层形成其制造方法 以及外围电路区域PMOS的栅电极，并且通过在外围电路区域NMOS的栅电极上形成包括多晶硅层和第二金属层的多层。 由于多层栅电极，不需要单独的瞬态离子注入工艺，从而简化了CMOS制造工艺，同时保持了每个外围电路区域的阈值电压为-0.5V及以下，外围电路的阈值电压 电路区域NMOS + 0.5V及以下。 同时，由于单元NMOS由于第一金属层而具有+ 1V的阈值电压，因此不需要单独的背偏置，从而形成具有低功耗的器件，从而提高器件的特性，产量和可靠性。

公开(公告)号：US06448166B2

公开(公告)日：2002-09-10

申请号：US09895268

申请日：2001-07-02

申请人： Heung Jae Cho ,  Dae Gyu Park ,  Kwan Yong Lim

发明人： Heung Jae Cho ,  Dae Gyu Park ,  Kwan Yong Lim

IPC分类号： H01L213205

CPC分类号： H01L21/02356 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02183 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaOxNy film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO2 or SiON film on the semiconductor substrate, depositing an amorphous TaOxNy film on the SiO2 or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaOxNy film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaOxNy film, and crystallize the amorphous TaOxNy film, and depositing a metal barrier film on the crystallized TaOxNy film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.

摘要翻译： 本发明公开了一种通过沉积TaOxNy膜作为栅氧化膜形成半导体器件的栅极的方法。 该方法包括以下步骤：提供半导体衬底，其中已经形成器件隔离膜，在半导体衬底上生长SiO 2或SiON膜，在SiO 2或SiON膜上沉积无定形TaO x N y膜，进行低温退火工艺以改善 无定形TaOxNy膜的质量，非晶态TaO x N y膜中的有机物质和氮气的去除，进行高温退火处理，使无定形TaO x N y膜结晶化，在结晶化的TaO x N y膜上沉积金属阻挡膜， 多晶硅膜或用于金属阻挡膜上的栅电极的金属膜。