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    Current sense trench type MOSFET with improved accuracy and ESD withstand capability
    2.
    发明申请
    Current sense trench type MOSFET with improved accuracy and ESD withstand capability 有权
    电流检测沟槽型MOSFET具有改进的精度和ESD承受能力

    公开(公告)号：US20050174823A1

    公开(公告)日：2005-08-11

    申请号：US11066178

    申请日：2005-01-31

    申请人： Jianjun Cao ,  Ying Xiao ,  Kyle Spring ,  Daniel Kinzer

    发明人： Jianjun Cao ,  Ying Xiao ,  Kyle Spring ,  Daniel Kinzer

    IPC分类号： G11C5/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813

    摘要： The active area of a current sense die is surrounded by a transition region which extends to the terminating periphery of the die. Spaced parallel MOSgated trenches extend through and define an active area. The trench positions in the transition region are eliminated or are deactivated, as by shorting to the MOSFET source of the trench, or by removing the source regions in areas of the transition region. By inactivating MOSgate action in the transition region surrounding the source, the device is made less sensitive to current ratio variation due to varying manufacturing tolerances. The gate to source capacitance is increased by surrounding the active area with an enlarged P+ field region which is at least five times the area of the active region, thereby to make the device less sensitive to ESD failure.

    摘要翻译： 电流感测管芯的有源区域被延伸到管芯的端部周边的过渡区域包围。 间距平行的MOS沟槽延伸通过并定义有效区域。 过渡区域中的沟槽位置被消除或被去激活，如通过短路到MOSFET的MOSFET源，或者通过去除过渡区域的区域中的源极区域。 通过使围绕源极的过渡区域中的MOSgate动作失效，由于变化的制造公差，该器件对电流比率变化的敏感度较低。 栅极到源极电容通过围绕有源区域而增加，其具有至少是有源区域面积的五倍的扩大的P + SUPER场区域，从而使得该器件对ESD故障较不敏感。

    MOSFET with reduced threshold voltage and on resistance and process for its manufacture
    3.
    发明授权
    MOSFET with reduced threshold voltage and on resistance and process for its manufacture 有权
    MOSFET具有降低的阈值电压和电阻及其制造工艺

    公开(公告)号：US06781203B2

    公开(公告)日：2004-08-24

    申请号：US10044427

    申请日：2001-11-09

    申请人： Thomas Herman ,  Harold Davis ,  Kyle Spring ,  Jianjun Cao

    发明人： Thomas Herman ,  Harold Davis ,  Kyle Spring ,  Jianjun Cao

    IPC分类号： H01L2946

    CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/41766

    摘要： A vertical conduction MOSFET having a reduced on resistance RDSON as well as reduced threshold voltage Vth, and an improved resistance to punchthrough and walkout has an extremely shallow source diffusion, of less than 0.3 microns in depth and an extremely shallow channel diffusion, of less than about 3 microns in depth. In a P channel version, phosphorus is implanted into the bottom of a contact trench and into the channel region with an implant energy of 400 keV for a singly charged phosphorus ion or 200 keV for a doubly charged ion, thereby to prevent walkout of the threshold voltage.

    摘要翻译： 具有降低的导通电阻RDSON和降低的阈值电压Vth的垂直导通MOSFET以及改进的穿通和迂回阻力具有小于0.3微米深度的极浅源极扩散和小于0.3微米的通道扩散。 约3微米深。 在P沟道版本中，磷被注入到接触沟槽的底部并且注入到沟道区域中，对于单电荷的磷离子或200keV的注入能量为400keV，用于双电荷离子，从而防止阈值 电压。

    Power MOSFET with ultra-deep base and reduced on resistance
    5.
    发明授权
    Power MOSFET with ultra-deep base and reduced on resistance 有权
    功率MOSFET具有超深基极和降低导通电阻

    公开(公告)号：US06639276B2

    公开(公告)日：2003-10-28

    申请号：US10187580

    申请日：2002-07-01

    申请人： Kyle Spring ,  Jianjun Cao

    发明人： Kyle Spring ,  Jianjun Cao

    IPC分类号： H01L31113

    CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/66719

    摘要： A power semiconductor device formed of a substrate of a first conductivity type, an epitaxial layer of a first conductivity type formed on a surface of the substrate, a plurality of lightly doped spaced base regions of a second conductivity type formed to a first predetermined depth in the epitaxial layer with common conduction regions between the base regions, a plurality of highly doped source regions of the first conductivity type formed in the lightly doped base regions, invertible channel regions disposed between the source regions and the common conduction regions, deep implanted junctions of the second conductivity type formed in the epitaxial layer under the base regions extending between the first predetermined depth and a second predetermined depth, gate electrodes insulated from the invertible channels by an insulation layer formed over the invertible channels, and thick insulation spacers disposed over at least a portion of the common conduction regions.

    摘要翻译： 一种由第一导电类型的衬底形成的功率半导体器件，形成在衬底的表面上的第一导电类型的外延层，第二导电类型的多个轻掺杂间隔的基极区域形成为第一预定深度 在基极区域之间具有共同导电区域的外延层，形成在轻掺杂基极区域中的第一导电类型的多个高掺杂源极区域，设置在源区域和公共导电区域之间的可逆沟道区域， 形成在第一预定深度和第二预定深度之间的基底区域之下的外延层中的第二导电类型，通过形成在可逆通道上的绝缘层与可逆通道绝缘的栅极电极以及至少设置在绝缘层上的厚绝缘间隔物 一部分共同导电区域。

    Current sense trench type MOSFET with improved accuracy and ESD withstand capability
    6.
    发明授权
    Current sense trench type MOSFET with improved accuracy and ESD withstand capability 有权
    电流检测沟槽型MOSFET具有改进的精度和ESD承受能力

    公开(公告)号：US07619280B2

    公开(公告)日：2009-11-17

    申请号：US11066178

    申请日：2005-01-31

    申请人： Jianjun Cao ,  Ying Xiao ,  Kyle Spring ,  Daniel M. Kinzer

    发明人： Jianjun Cao ,  Ying Xiao ,  Kyle Spring ,  Daniel M. Kinzer

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7811 ,  H01L29/7813

    摘要： The active area of a current sense die is surrounded by a transition region which extends to the terminating periphery of the die. Spaced parallel MOSgated trenches extend through and define an active area. The trench positions in the transition region are eliminated or are deactivated, as by shorting to the MOSFET source of the trench, or by removing the source regions in areas of the transition region. By inactivating MOSgate action in the transition region surrounding the source, the device is made less sensitive to current ratio variation due to varying manufacturing tolerances. The gate to source capacitance is increased by surrounding the active area with an enlarged P+ field region which is at least five times the area of the active region, thereby to make the device less sensitive to ESD failure.

    摘要翻译： 电流感测管芯的有源区域被延伸到管芯的端部周边的过渡区域包围。 间距平行的MOS沟槽延伸通过并定义有效区域。 过渡区域中的沟槽位置被消除或被去激活，如通过短路到MOSFET的MOSFET源，或者通过去除过渡区域的区域中的源极区域。 通过使围绕源极的过渡区域中的MOSgate动作失效，由于变化的制造公差，该器件对电流比率变化的敏感度较低。 通过用有源区域的面积的至少五倍的扩大的P +场区域围绕有源区域来增加栅极到源极电容，从而使得器件对ESD故障较不敏感。

    Trench power MOSFET fabrication using inside/outside spacers
    7.
    发明授权
    Trench power MOSFET fabrication using inside/outside spacers 有权
    沟槽功率MOSFET制造使用内/外隔板

    公开(公告)号：US07390717B2

    公开(公告)日：2008-06-24

    申请号：US11054451

    申请日：2005-02-09

    申请人： Jianjun Cao ,  Paul Harvey ,  David Kent ,  Robert Montgomery ,  Kyle Spring

    发明人： Jianjun Cao ,  Paul Harvey ,  David Kent ,  Robert Montgomery ,  Kyle Spring

    IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/20

    CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

    摘要： A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

    摘要翻译： 用于沟槽型功率半导体器件的制造工艺包括在半导体表面上形成间隔物内部。 使用间隔物作为掩模，在半导体本体中形成具有栅极的沟槽。 在去除间隔物之后，沿着沟槽边缘在半导体本体中形成源植入物，然后被驱动。 然后在沟槽上形成绝缘帽。 接下来沿着盖的侧面形成外部间隔物。 使用这些间隔物作为掩模，蚀刻半导体表面并形成高导电性接触区域。 然后移除外部隔离物并形成源极和漏极接触。 或者，源植入物不被驱动。 相反，在外部间隔物形成之前，执行第二源植入。 然后形成外部间隔物，蚀刻第二源植入物的部分，驱动所有剩余的源植入物和形成的接触区域。 栅极电极在半导体表面之下凹进或延伸。

    Trench power MOSFET fabrication using inside/outside spacers
    8.
    发明申请
    Trench power MOSFET fabrication using inside/outside spacers 有权
    沟槽功率MOSFET制造使用内/外隔板

    公开(公告)号：US20050208724A1

    公开(公告)日：2005-09-22

    申请号：US11054451

    申请日：2005-02-09

    申请人： Jianjun Cao ,  Paul Harvey ,  David Kent ,  Robert Montgomery ,  Kyle Spring

    发明人： Jianjun Cao ,  Paul Harvey ,  David Kent ,  Robert Montgomery ,  Kyle Spring

    IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

    摘要： A fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.

    摘要翻译： 用于沟槽型功率半导体器件的制造工艺包括在半导体表面上形成间隔物内部。 使用间隔物作为掩模，在半导体本体中形成具有栅极的沟槽。 在去除间隔物之后，沿着沟槽边缘在半导体本体中形成源植入物，然后被驱动。 然后在沟槽上形成绝缘帽。 接下来沿着盖的侧面形成外部间隔物。 使用这些间隔物作为掩模，蚀刻半导体表面并形成高导电性接触区域。 然后移除外部隔离物并形成源极和漏极接触。 或者，源植入物不被驱动。 相反，在外部间隔物形成之前，执行第二源植入。 然后形成外部间隔物，蚀刻第二源植入物的部分，驱动所有剩余的源植入物和形成的接触区域。 栅极电极在半导体表面之下凹进或延伸。