公开(公告)号：US08233698B2

公开(公告)日：2012-07-31

申请号：US11971550

申请日：2008-01-09

申请人： Kyoji Yamashita

发明人： Kyoji Yamashita

IPC分类号： G06K9/00

CPC分类号： G06K9/32 ,  G01N21/95607 ,  G03F1/84 ,  G06T7/001 ,  G06T7/32 ,  G06T2207/10056 ,  G06T2207/30148

摘要： A pattern inspection apparatus includes a first unit configured to acquire an optical image of a target workpiece to be inspected, a second unit configured to generate a reference image to be compared, a third unit configured, by using a mathematical model in which a parallel shift amount, an expansion and contraction error coefficient, a rotation error coefficient, a gray-level offset and an image transmission loss ratio are parameters, to calculate each of the parameters by a least-squares method, a forth unit configured to generate a corrected image by shifting a position of the reference image by a displacement amount, based on the each of the parameters, and a fifth unit configured to compare the corrected image with the optical image.

摘要翻译： 图案检查装置包括被配置为获取要检查的目标工件的光学图像的第一单元，被配置为生成要比较的参考图像的第二单元，第三单元，其被配置为使用数学模型，其中并行移位 数量，膨胀和收缩误差系数，旋转误差系数，灰度偏移和图像传输损耗比是参数，以最小二乘法计算每个参数;第四单元，被配置为生成校正图像 通过基于每个参数移动参考图像的位置位移量，以及被配置为将校正图像与光学图像进行比较的第五单元。

公开(公告)号：US07421109B2

公开(公告)日：2008-09-02

申请号：US10642760

申请日：2003-08-19

申请人： Hideo Tsuchiya ,  Kyoji Yamashita ,  Toshiyuki Watanabe ,  Ikunao Isomura ,  Toru Tojo ,  Yasushi Sanada

发明人： Hideo Tsuchiya ,  Kyoji Yamashita ,  Toshiyuki Watanabe ,  Ikunao Isomura ,  Toru Tojo ,  Yasushi Sanada

IPC分类号： G06K9/00 ,  G01B11/00 ,  G01J1/10

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： A pattern inspecting method, comprising preparing a sample having a first and a second inspection regions and an imaging device having a plurality of pixels, scanning the first inspection region to a first direction using the imaging device to obtain a first measurement pattern representing at least parts of the first inspection region, scanning the second inspection region to the first direction using the imaging device to obtain a second measurement pattern representing at least parts of the second inspection region, comparing the first measurement pattern and the second measurement pattern with each other to determine presence or absence of a defect formed on the sample, and controlling a scanning condition for scanning a pattern of the second inspection region by the imaging device so as to keep the same with the scanning condition when the pattern of the first inspection region is scanned by the imaging device.

摘要翻译： 一种图案检查方法，包括准备具有第一和第二检查区域的样本和具有多个像素的成像装置，使用成像装置将第一检查区域扫描到第一方向，以获得表示至少部分的第一测量图案 使用所述成像装置将所述第二检查区域扫描到所述第一方向，以获得表示所述第二检查区域的至少一部分的第二测量图案，将所述第一测量图案和所述第二测量图案彼此进行比较，以确定 存在或不存在形成在样品上的缺陷，以及控制用于通过成像装置扫描第二检查区域的图案的扫描条件，以便当第一检查区域的图案被扫描时与扫描条件保持相同 成像装置。

公开(公告)号：US20080142898A1

公开(公告)日：2008-06-19

申请号：US11979669

申请日：2007-11-07

申请人： Shinji Watanabe ,  Daisaku Ikoma ,  Kyoji Yamashita ,  Katsuhiro Ootani

发明人： Shinji Watanabe ,  Daisaku Ikoma ,  Kyoji Yamashita ,  Katsuhiro Ootani

IPC分类号： H01L27/092

CPC分类号： H01L27/0207 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0922

摘要： An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.

摘要翻译： 集成电路包括：第一导电类型的第一阱; 第二导电类型的第二阱在沿栅极长度方向延伸的阱边界处与第一阱接触; 第一晶体管，具有设置在第一阱中的第二导电类型的第一有源区; 以及第二晶体管，其具有设置在第一阱中的第二导电类型的第二有源区，并且与栅极宽度方向上的第一有源区的长度不同。 第一有源区域在栅极宽度方向上的中心位置与第二有源区域相对于阱边界在栅极宽度方向上的中心位置对准。

公开(公告)号：US20080042214A1

公开(公告)日：2008-02-21

申请号：US11892053

申请日：2007-08-20

申请人： Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

发明人： Daisaku Ikoma ,  Atsuhiro Kajiya ,  Katsuhiro Ootani ,  Kyoji Yamashita

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/823475 ,  H01L27/0207

摘要： A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

摘要翻译： 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。

公开(公告)号：US20070100807A1

公开(公告)日：2007-05-03

申请号：US11553711

申请日：2006-10-27

申请人： Kazuko Abe ,  Junichi Yamamoto ,  Rei Yano ,  Masataka Yamada ,  Yasuhide Kurosaki ,  Michiyo Ikegami ,  Kyoji Yamashita ,  Kouji Gouda

发明人： Kazuko Abe ,  Junichi Yamamoto ,  Rei Yano ,  Masataka Yamada ,  Yasuhide Kurosaki ,  Michiyo Ikegami ,  Kyoji Yamashita ,  Kouji Gouda

IPC分类号： G06F17/30

CPC分类号： G06F17/30964 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99953

摘要： A data searching unit 12 of a data searching apparatus 10 obtains according to a searching request including a search condition specified by a data searching application 16, metadata which satisfy the search condition from a data storage unit 11, and instructs an external communication unit 15 to request searching of data to a data providing apparatus 20 with the same search condition.

摘要翻译： 数据搜索装置10的数据搜索单元12根据包括由数据搜索应用16指定的搜索条件的搜索请求获得满足来自数据存储单元11的搜索条件的元数据，并且指示外部通信单元15 请求搜索具有相同搜索条件的数据到数据提供装置20。

公开(公告)号：US20060282249A1

公开(公告)日：2006-12-14

申请号：US11349077

申请日：2006-02-08

申请人： Daisaku Ikoma ,  Kyoji Yamashita ,  Katsuhiro Ootani

发明人： Daisaku Ikoma ,  Kyoji Yamashita ,  Katsuhiro Ootani

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In designing a semiconductor integrated circuit, circuit information used for circuit simulation is extracted from measurement values of electric characteristics of a device included in TEG and parameters included in a netlist are modified using the measurement values and simulation values. Circuit simulation is carried out using the thus modified netlist to lead to a decrease in error in the circuit simulation which is caused due to difference between design dimension and actual finished dimension, thereby preventing an increase in design margin and a yield lowering by malfunction.

摘要翻译： 在设计半导体集成电路时，从包含在TEG中的设备的电特性的测量值中提取用于电路仿真的电路信息，并且使用测量值和模拟值来修改网表中包括的参数。 使用如此修改的网表进行电路仿真，导致由于设计尺寸和实际成品尺寸之间的差异导致的电路仿真中的误差减小，从而防止设计裕度增加和故障产生降低。

公开(公告)号：US06982555B2

公开(公告)日：2006-01-03

申请号：US10777068

申请日：2004-02-13

申请人： Kyoji Yamashita ,  Tatsuya Kunikiyo ,  Tetsuya Watanabe ,  Toshiki Kanamoto

发明人： Kyoji Yamashita ,  Tatsuya Kunikiyo ,  Tetsuya Watanabe ,  Toshiki Kanamoto

IPC分类号： G01R31/08 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： PMISFETs and NMISFETs are placed in a capacitance measuring circuit. Each of interconnects is connected via the corresponding PMISFET through a charging voltage supply part to a power supply pad and via the corresponding NMISFET through a current sampling part to a current-monitoring pad. A current I can be measured by bringing a probe of an ammeter into contact with the current-monitoring pad.

摘要翻译： PMISFET和NMISFET放置在电容测量电路中。 每个互连通过相应的PMISFET通过充电电压供应部分连接到电源焊盘，并通过相应的NMISFET通过电流采样部分连接到电流监测焊盘。 可以通过将电流表的探头与电流监测板接触来测量电流。

公开(公告)号：US06894520B2

公开(公告)日：2005-05-17

申请号：US10355068

申请日：2003-01-31

申请人： Kyoji Yamashita ,  Hiroyuki Umimoto ,  Mutsumi Kobayashi ,  Katsuhiro Ohtani ,  Tatsuya Kunikiyo ,  Katsumi Eikyu

发明人： Kyoji Yamashita ,  Hiroyuki Umimoto ,  Mutsumi Kobayashi ,  Katsuhiro Ohtani ,  Tatsuya Kunikiyo ,  Katsumi Eikyu

IPC分类号： G01R27/26 ,  G01R31/27 ,  G01R31/28 ,  G01R31/312 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G01R31/26

CPC分类号： G01R31/275 ,  G01R31/312

摘要： A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

摘要翻译： CBCM测量装置包括PMIS晶体管，NMIS晶体管，连接到第一节点的第一参考导体部分，在第一和第二参考导体部分之间形成有虚拟电容器的第二参考导体部分，第一测试导体部分 连接到第二节点和第二测试导体部分，其中测试电容器形成在第一和第二测试导体部分之间。 通过使用控制电压V 1和V 2将晶体管导通/截止，并且基于流过第一和第二节点的电流来测量测试电容器中的目标电容器的电容。 通过例如增加虚拟电容来提高电容测量精度。

公开(公告)号：US5185812A

公开(公告)日：1993-02-09

申请号：US653236

申请日：1991-02-11

申请人： Kyoji Yamashita ,  Ryoichi Yoshikawa ,  Masakazu Tokita

发明人： Kyoji Yamashita ,  Ryoichi Yoshikawa ,  Masakazu Tokita

IPC分类号： G06K9/64 ,  G06T7/00

CPC分类号： G06T7/001 ,  G06K9/6202 ,  G06T2207/30148

摘要： A pattern inspection apparatus comprises a sensor data input section for inputting a two-dimensional inspected pattern as image data (sensor data) having a multivalued (non-binary) density distribution, design data input section for inputting reference pattern data (reference data) corresponding to the inspected pattern, a compare section for making a comparison between the image data and the reference data to obtain the difference in density therebeween, a minimum compare section for performing spatial differentiation filtering on the distribution of density between the inspected pattern and the reference pattern in different directions and obtaining the minimum of the absolute values of the filtered outputs, and a first defect determining section for detecting a defect on the basis of the minimum obtained by the compare section. In place of the first defect determining section, a maximum/minimum compare section for obtaining the minimum and maximum of the absolute values of the filtered outputs and a second defect determining section for detecting a defect on the basis of the density difference, the minimum and the maximum may be provided.

摘要翻译： 图案检查装置包括用于输入二维检查图案的传感器数据输入部分作为具有多值（非二进制）密度分布的图像数据（传感器数据），设计数据输入部分，用于输入相应的参考图案数据（参考数据） 检查图案的比较部分，用于对图像数据和参考数据进行比较以获得其密度差的比较部分，用于对被检查图案和参考图案之间的密度分布进行空间微分滤波的最小比较部分 并且获得滤波输出的绝对值的最小值;以及第一缺陷确定部分，用于基于由比较部分获得的最小值来检测缺陷。 代替第一缺陷确定部分，用于获得滤波输出的绝对值的最小值和最大值的最大/最小比较部分和用于基于密度差检测缺陷的第二缺陷确定部分， 可以提供最大值。

公开(公告)号：US08013361B2

公开(公告)日：2011-09-06

申请号：US11270602

申请日：2005-11-10

申请人： Kyoji Yamashita ,  Katsuhiro Otani ,  Katsuya Arai ,  Daisaku Ikoma

发明人： Kyoji Yamashita ,  Katsuhiro Otani ,  Katsuya Arai ,  Daisaku Ikoma

IPC分类号： H01L27/118

CPC分类号： H01L29/78 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/11807 ,  H01L29/4238

摘要： Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

摘要翻译： 栅电极5A至5F形成为具有相同的几何形状，并且栅电极5A至5F的突出部分跨越隔离区延伸到杂质扩散区上。 栅电极5B和P型杂质扩散区7B6通过共用触点9A1连接到第一级布线M1H，栅电极5E和N型杂质扩散区7A6通过共用触点9A2连接到第一级 级互连M1I。 以这种方式，栅电极5A至5F的接触焊盘部分可以位于用于MOS晶体管的衬底的有源区域之外。 这抑制了由于锤头和栅极扩孔引起的栅极长度增加的影响。 结果，晶体管TrA至TrF可以具有基本相同的精加工栅极长度。