公开(公告)号：US20090090942A1

公开(公告)日：2009-04-09

申请号：US12231709

申请日：2008-09-04

申请人： Kyong-Sub Kim ,  Sang-Un Nam ,  Chang-Oh Jeong ,  Weon-Sik Oh ,  Sung-Lak Choi ,  Soo-Im Jeong ,  Jae-Ho Eo

发明人： Kyong-Sub Kim ,  Sang-Un Nam ,  Chang-Oh Jeong ,  Weon-Sik Oh ,  Sung-Lak Choi ,  Soo-Im Jeong ,  Jae-Ho Eo

IPC分类号： H01L29/786 ,  H01B5/14 ,  B05D5/12 ,  H01L21/336

CPC分类号： H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A wiring structure includes a substrate, a copper oxide layer having 16˜39 at % oxygen on the substrate and a copper layer on the copper oxide layer. The copper oxide layer has a thickness of 10-1000 Å and the copper layer has a thickness of 300-8000 Å. The copper layer and the copper oxide layer further have an alloy element less than 10 wt % and the alloy element is selected from the group of Ag, Ni, Mg, Zr, N.

摘要翻译： 布线结构包括基板，在基板上具有16〜39at％的氧的氧化铜层和氧化铜层上的铜层。 铜氧化物层的厚度为10-1000埃，铜层的厚度为300-8000埃。 铜层和氧化铜层还具有小于10重量％的合金元素，合金元素选自Ag，Ni，Mg，Zr，N组。

公开(公告)号：US08551307B2

公开(公告)日：2013-10-08

申请号：US12779459

申请日：2010-05-13

申请人： Do-Hyun Kim ,  Dong-Hoon Lee ,  Chang-Oh Jeong

发明人： Do-Hyun Kim ,  Dong-Hoon Lee ,  Chang-Oh Jeong

IPC分类号： C23C14/34

CPC分类号： C23C14/3407 ,  C23C14/3464 ,  H01J37/342 ,  H01J37/3435

摘要： A sputtering target apparatus is provided. The sputtering target apparatus includes a first target assembly including a first target array having a first target, a second target disposed adjacent to the first target, and a first target dividing region disposed between the first and second targets, the first target assembly extending along a first direction, wherein the first target dividing region has a longitudinal cross-section that is oblique with respect to the first direction.

摘要翻译： 提供溅射靶设备。 溅射靶设备包括：第一目标组件，其包括具有第一靶的第一靶阵列，与第一靶相邻设置的第二靶;以及设置在第一靶和第二靶之间的第一靶分离区， 第一方向，其中第一目标分割区域具有相对于第一方向倾斜的纵向横截面。

公开(公告)号：US08455871B2

公开(公告)日：2013-06-04

申请号：US12859792

申请日：2010-08-20

申请人： Chang-Oh Jeong ,  Woo-Sung Sohn ,  Dong-Gyu Kim ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jean-Ho Song

发明人： Chang-Oh Jeong ,  Woo-Sung Sohn ,  Dong-Gyu Kim ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jean-Ho Song

IPC分类号： H01L29/04

CPC分类号： H01L33/16 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

公开(公告)号：US08207534B2

公开(公告)日：2012-06-26

申请号：US12417280

申请日：2009-04-02

申请人： Je-Hun Lee ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L29/786

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

公开(公告)号：US20110284857A1

公开(公告)日：2011-11-24

申请号：US13204553

申请日：2011-08-05

申请人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L27/088 ,  H01L21/84

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

公开(公告)号：US07919795B2

公开(公告)日：2011-04-05

申请号：US11961149

申请日：2007-12-20

申请人： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

发明人： Je-Hun Lee ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L29/43 ,  H01L29/49 ,  H01L33/00

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/4908

摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.

摘要翻译： 提供线结构，制造线的方法，薄膜晶体管（TFT）基板和制造TFT基板的方法。 导线结构包括形成在基板上并包括铜，铜固溶体层的阻挡层。

公开(公告)号：US20110065220A1

公开(公告)日：2011-03-17

申请号：US12951981

申请日：2010-11-22

申请人： Je-Hun LEE ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun LEE ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

公开(公告)号：US07858982B2

公开(公告)日：2010-12-28

申请号：US11215067

申请日：2005-08-29

申请人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

公开(公告)号：US07741641B2

公开(公告)日：2010-06-22

申请号：US11371057

申请日：2006-03-08

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L29/43 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.

摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。 栅极布线包括栅极线和栅电极。 栅极绝缘层形成在基底基板上以覆盖栅极布线。 活化层形成在栅绝缘层上。 氧化阻挡层形成在活化层上。 数据线包括数据线，源电极和漏电极。 源电极和漏电极设置在氧化阻挡层上，因此降低用于导通TFT的导通电流（“Ion”），并且由于氧化阻挡层而增加关闭TFT的截止电流（“Ioff”）， 阻挡层。

公开(公告)号：US07619254B2

公开(公告)日：2009-11-17

申请号：US11228852

申请日：2005-09-16

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。