公开(公告)号：US07110289B1

公开(公告)日：2006-09-19

申请号：US10816271

申请日：2004-03-31

申请人： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

发明人： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

IPC分类号： G11C11/15

CPC分类号： G11C11/15

摘要： In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

摘要翻译： 在用于减少由磁存储器消耗的功率的方法和系统中，磁存储器单元耦合到位线并与多个数字线相关联。 位线中提供位线电流。 与位线电流基本相同的时刻，在数字线中并联提供数字电流。 数字和位线电流允许磁存储单元被并行写入多个状态。

公开(公告)号：US07012832B1

公开(公告)日：2006-03-14

申请号：US10698747

申请日：2003-10-31

申请人： Kyusik Sin ,  Matthew R. Gibbons ,  William D. Jensen ,  Hugh Craig Hiner ,  Xizeng Stone Shi ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappelletti

发明人： Kyusik Sin ,  Matthew R. Gibbons ,  William D. Jensen ,  Hugh Craig Hiner ,  Xizeng Stone Shi ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappelletti

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic random access memory (MRAM) device has increased ΔR/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ΔR/R. The plural transistors can share a source region.

摘要翻译： 磁性随机存取存储器（MRAM）器件增加了用于感测引脚依赖隧道（SDT）器件的状态的DeltaR / R。 MRAM器件包括连接到读取线的多个晶体管，用于感测SDT器件的状态。 多个晶体管在读取期间降低潜在电阻，增加DeltaR / R。 多个晶体管可以共享源极区域。

公开(公告)号：US20060049391A1

公开(公告)日：2006-03-09

申请号：US11258340

申请日：2005-10-24

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： H01L47/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US07372166B2

公开(公告)日：2008-05-13

申请号：US11258340

申请日：2005-10-24

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： H01L23/48

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US07135756B2

公开(公告)日：2006-11-14

申请号：US10680727

申请日：2003-10-07

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L27/102

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US06972430B2

公开(公告)日：2005-12-06

申请号：US10371154

申请日：2003-02-20

申请人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

发明人： Giulio Casagrande ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

摘要翻译： 电子半导体器件具有在第一导电区域和第二导电区域之间的亚光刻接触面积。 第一导电区域是杯状的并且具有垂直壁，其在顶部平面图中沿着细长形状的封闭线延伸。 第一导电区域的一个壁形成第一薄部分并且具有在第一方向上的第一尺寸。 第二导电区域具有第二薄部分，该第二薄部分具有横向于第一尺寸的第二方向的第二亚光刻尺寸。 第一和第二导电区域在其薄部分处直接电接触并形成亚光刻接触区域。 细长形状选择在第一方向上伸长的矩形和椭圆形之间。 因此，即使在限定导电区域的掩模之间存在小的不对准的情况下，接触区域的尺寸也保持近似恒定。

公开(公告)号：US06567296B1

公开(公告)日：2003-05-20

申请号：US10041684

申请日：2001-10-24

申请人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

发明人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

IPC分类号： G11C1706

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

摘要： A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

摘要翻译： 一种存储器件，包括多个存储器单元，形成在半导体材料的芯片中的第一类型的导电性的多个绝缘的第一区域，在每个第一区域中形成的至少一个第二导电类型的第二区域， 每个第二区域和相应的第一区域限定单向传导访问元件，用于当正向偏置时选择连接到第二区域的对应的存储单元，以及用于接触每个第一区域的至少一个触点; 在每个第一区域中形成多个访问元件，所述访问元件被分组成由多个相邻的访问元件组成的至少一个子集，而不插入任何联系人，并且所述存储器设备还包括： 每个子集的元素同时进行。

公开(公告)号：US07446011B2

公开(公告)日：2008-11-04

申请号：US11551170

申请日：2006-10-19

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L21/8222

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US20070099347A1

公开(公告)日：2007-05-03

申请号：US11551170

申请日：2006-10-19

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

IPC分类号： H01L21/00

CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

摘要： A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

摘要翻译： 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

公开(公告)号：US20120113711A1

公开(公告)日：2012-05-10

申请号：US13353531

申请日：2012-01-19

申请人： Tyler Lowrey ,  Ward D. Parkinson ,  Ferdinando Bedeschi ,  Claudio Resta ,  Roberto Gastaldi ,  Giulio Casagrande

发明人： Tyler Lowrey ,  Ward D. Parkinson ,  Ferdinando Bedeschi ,  Claudio Resta ,  Roberto Gastaldi ,  Giulio Casagrande

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments,

摘要翻译： 在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。 因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。 在一些实施例中，可以改善所得到的读取窗口或边缘，