公开(公告)号：US07110289B1

公开(公告)日：2006-09-19

申请号：US10816271

申请日：2004-03-31

申请人： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

发明人： Kyusik Sin ,  Hugh Craig Hiner ,  Xizeng (Stone) Shi ,  William D. Jensen ,  Hua-Ching Tong ,  Matthew R Gibbons ,  Roberto Bez ,  Giulio Casagrande ,  Paolo Cappeletti ,  Marco Pasotti

IPC分类号： G11C11/15

CPC分类号： G11C11/15

摘要： In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

摘要翻译： 在用于减少由磁存储器消耗的功率的方法和系统中，磁存储器单元耦合到位线并与多个数字线相关联。 位线中提供位线电流。 与位线电流基本相同的时刻，在数字线中并联提供数字电流。 数字和位线电流允许磁存储单元被并行写入多个状态。

公开(公告)号：US08264872B2

公开(公告)日：2012-09-11

申请号：US12548241

申请日：2009-08-26

申请人： Guido De Sandre ,  Marco Pasotti

发明人： Guido De Sandre ,  Marco Pasotti

IPC分类号： G11C11/00 ,  G11C8/10 ,  G11C7/00

CPC分类号： G11C13/0026 ,  G11C13/0004

摘要： A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

摘要翻译： 列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。 列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。 在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径， 在位线和编程阶段之间。

公开(公告)号：US07843255B2

公开(公告)日：2010-11-30

申请号：US11966117

申请日：2007-12-28

申请人： Marco Poles ,  Marco Pasotti

发明人： Marco Poles ,  Marco Pasotti

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M1/14

摘要： There is disclosed a regulator for a charge pump having an input signal and generating an output signal at a value greater than the input signal. The charge pump comprises at least a capacitor and at least a device for charging and discharging the capacitor; the regulator comprises means having at the input said signal exiting the charge pump and a reference signal. Said means are able to generate a supply signal for said at least a device in response to the value of the difference between the output signal of the charge pump and said reference signal.

摘要翻译： 公开了一种具有输入信号并且以大于输入信号的值产生输出信号的电荷泵的调节器。 电荷泵至少包括一个电容器和至少一个用于充电和放电电容器的装置; 调节器包括在输入处具有离开电荷泵的信号和参考信号的装置。 所述装置能够响应于电荷泵的输出信号与所述参考信号之间的差值而产生用于所述至少一个装置的电源信号。

公开(公告)号：US07504862B2

公开(公告)日：2009-03-17

申请号：US11321732

申请日：2005-12-28

申请人： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

发明人： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528 ,  H03K19/01707 ,  H03K19/01721

摘要： Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

摘要翻译： 该类型的电平移位器转换器包括至少一个第一晶体管和一个第二MOS晶体管，属于与第一公共导通端子连接并连接到第一电位基准的相应电路分支，并且在相应的导通端子上接收输入差分电压， 第一晶体管和第二晶体管具有指向具有电流镜的偏置电路的各个电路分支，第三晶体管允许将第二晶体管耦合到所述偏置电路，反相器连接到所述电路的输出端，输出驱动第三晶体管。

公开(公告)号：US06687167B2

公开(公告)日：2004-02-03

申请号：US10225513

申请日：2002-08-20

申请人： Giovanni Guaitini ,  Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pier Luigi Rolandi

发明人： Giovanni Guaitini ,  Marco Pasotti ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pier Luigi Rolandi

IPC分类号： G11C1604

CPC分类号： G11C16/08 ,  G11C16/16

摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

摘要翻译： 一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。 每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。 为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和 下分支。 以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为 下拉和下部分支作为上拉。

公开(公告)号：US06687159B2

公开(公告)日：2004-02-03

申请号：US10036337

申请日：2001-12-19

申请人： Marco Pasotti ,  Giovanni Guaitini ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pierluigi Rolandi

发明人： Marco Pasotti ,  Giovanni Guaitini ,  Guido De Sandre ,  David Iezzi ,  Marco Poles ,  Pierluigi Rolandi

IPC分类号： G11C1604

CPC分类号： G11C16/3481 ,  G11C8/08 ,  G11C16/12

摘要： A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.

摘要翻译： 一种编程多个存储单元的方法并联连接在第一和第二供电基准之间，并且其栅极端子连接在一起，并且通过行解码装置也连接到适于产生字的运算放大器的输出端 电压信号，第一参考电压由电荷泵电路提供。 编程方法使用包括要编程的单元和运算放大器的程序循环，电荷泵电路因此输出其斜率是单元需求函数的电压斜坡。 还提供了一种适于实现该方法的编程电路。

公开(公告)号：US06581134B2

公开(公告)日：2003-06-17

申请号：US09817804

申请日：2001-03-26

申请人： Alessandro Rocchi ,  Marco Bisio ,  Marco Pasotti ,  Pier Luigi Rolandi

发明人： Alessandro Rocchi ,  Marco Bisio ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC分类号： G06F1200

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

摘要： A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

摘要翻译： FLASH存储器被组织在多个物理扇区中，这些扇区可以被分成多个可单独寻址的逻辑扇区。 每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。 如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值 ，如果数据已被擦除，则为第四个值。 此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。

公开(公告)号：US6091642A

公开(公告)日：2000-07-18

申请号：US234942

申请日：1999-01-21

申请人： Marco Pasotti ,  Roberto Canegallo ,  Ernestina Chioffi ,  Giovanni Guaitini ,  Frank Lhermet ,  Pierluigi Rolandi

发明人： Marco Pasotti ,  Roberto Canegallo ,  Ernestina Chioffi ,  Giovanni Guaitini ,  Frank Lhermet ,  Pierluigi Rolandi

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C27/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： G11C16/3409 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C27/005

摘要： The controlled erase method includes supplying at least one erase pulse to cells of a memory array; comparing the threshold voltage of the erased cells with a low threshold value; selectively soft-programming the erased cells which have a threshold voltage lower than the low threshold value; and verifying whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.

摘要翻译： 受控擦除方法包括向存储器阵列的单元提供至少一个擦除脉冲; 将擦除的单元的阈值电压与低阈值进行比较; 选择性地软编程具有低于低阈值的阈值电压的已擦除单元; 以及验证被擦除的单元是否具有低于低阈值的阈值电压。 如果至少一个预定数量的擦除单元具有高于高阈值的阈值电压，则将擦除脉冲施加到所有单元，并且重复比较选择性软编程和验证的步骤。

公开(公告)号：US08693256B2

公开(公告)日：2014-04-08

申请号：US12975055

申请日：2010-12-21

申请人： Marco Pasotti ,  Davide Lena ,  Fabio De Santis

发明人： Marco Pasotti ,  Davide Lena ,  Fabio De Santis

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0491 ,  G11C16/3418 ,  G11C2216/10

摘要： A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.

摘要翻译： 集成在半导体材料芯片中的非易失性存储器件。 存储器件的实施例包括多个存储器单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一导电类型的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二类型导电性的第一，第二和第三区域; 这些区域限定了串联耦合的MOS型选择晶体管和浮置栅极MOS型存储晶体管。 此外，存储器件包括选择晶体管的选择栅极，存储晶体管的浮置栅极和形成在第二阱中的存储晶体管的控制栅极; 控制栅极与浮动栅极电容耦合。

公开(公告)号：US08619469B2

公开(公告)日：2013-12-31

申请号：US12968522

申请日：2010-12-15

申请人： Marco Pasotti ,  Marcella Carissimi ,  Davide Lena

发明人： Marco Pasotti ,  Marcella Carissimi ,  Davide Lena

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C2216/10

摘要： An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are coupled in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.

摘要翻译： 提出了集成在半导体材料芯片中的非易失性存储器件的实施例。 存储装置包括多个存储单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一类导电性的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二导电类型的第一，第二，第三和第四区域; 这些区域限定了串联耦合的MOS型第一选择晶体管，浮栅MOS型存储晶体管和MOS型第二选择晶体管的序列。 第一个地区与第一个井短路。 此外，存储器件包括第一选择晶体管的第一栅极，第二选择晶体管的第二栅极和存储晶体管的浮置栅极。 存储晶体管的控制栅极形成在第二阱中; 控制栅极与浮动栅极电容耦合。