公开(公告)号：US20210225271A1

公开(公告)日：2021-07-22

申请号：US17224901

申请日：2021-04-07

Applicant: LG Display Co., Ltd.

Inventor： YongHo JANG ,  KwangIl CHUN

IPC: G09G3/32 ,  G09G3/3233

Abstract: A light emitting display apparatus includes a light emitting display panel including a plurality of pixels each operating in order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light emission period; a data driving circuit configured to supply data voltage to each of the pixels; a gate driving circuit configured to provide, to each of the pixels, a control signal having voltage levels determined for the initialization period, the sampling period, the offset voltage formation period, the data writing period, and the light emission period of a corresponding pixel; and a timing controller configured to control the data driving circuit and the gate driving circuit, wherein the offset voltage formation period is longer than the sampling period.

公开(公告)号：US20180190233A1

公开(公告)日：2018-07-05

申请号：US15830625

申请日：2017-12-04

Applicant: LG DISPLAY CO., LTD.

Inventor： YongHo JANG

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

Abstract: Disclosed are a shift register and a display device including the same, in which a size of a circuit is reduced. The shift register includes a stage outputting a gate shift clock, supplied through a gate shift clock line, as a scan pulse and outputting a carry shift clock, supplied through a carry shift clock line, as a carry pulse. The carry shift clock line overlaps the gate shift clock line.

公开(公告)号：US20180006056A1

公开(公告)日：2018-01-04

申请号：US15391636

申请日：2016-12-27

Applicant: LG Display Co., Ltd.

Inventor： JongUk BAE ,  YongHo JANG ,  JunHyeon BAE ,  Kwanghwan JI ,  PilSang YUN ,  Jiyong NOH

IPC: H01L27/12 ,  G02F1/1368 ,  H01L27/32 ,  G02F1/1362 ,  H01L29/786 ,  G09G3/36 ,  G09G3/3266 ,  G09G3/3258 ,  G09G3/3275

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0291 ,  G09G2310/08 ,  H01L27/3272 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: Disclosed are an oxide thin film transistor (TFT), a method of manufacturing the same, and a display panel and a display device using the same, in which a first conductor and a second conductor are provided at end portions of a semiconductor layer formed of oxide semiconductor. The first conductor and second conductor are electrically connected to a first electrode and a second electrode, and covered by a gate insulation layer. The oxide TFT includes a semiconductor layer provided on a buffer and including an oxide semiconductor, a gate insulation layer covering the semiconductor layer and the buffer, a gate electrode provided on the gate insulation layer to overlap a portion of the semiconductor layer, and a passivation layer covering the gate and the gate insulation layer.

公开(公告)号：US20190180675A1

公开(公告)日：2019-06-13

申请号：US16210587

申请日：2018-12-05

Applicant: LG Display Co., Ltd.

Inventor： YongHo JANG ,  KwangIl CHUN

IPC: G09G3/32

Abstract: A light emitting display apparatus includes a light emitting display panel including a plurality of pixels each operating in order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light emission period; a data driving circuit configured to supply data voltage to each of the pixels; a gate driving circuit configured to provide, to each of the pixels, a control signal having voltage levels determined for the initialization period, the sampling period, the offset voltage formation period, the data writing period, and the light emission period of a corresponding pixel; and a timing controller configured to control the data driving circuit and the gate driving circuit, wherein the offset voltage formation period is longer than the sampling period.

公开(公告)号：US20180366067A1

公开(公告)日：2018-12-20

申请号：US16005384

申请日：2018-06-11

Applicant: LG Display Co., Ltd.

Inventor： YongHo JANG

IPC: G09G3/3266 ,  G09G3/36 ,  G11C19/28

Abstract: Disclosed are a shift register and a display apparatus including the same, which stably output signals. The shift register may include a plurality of stages each including a first node controller controlling a voltage of a first node, based on first to third input signals and a transistor offset voltage. The first node controller may include a connection node supplied with at least one of the transistor offset voltage and the second input signal and preliminarily charged with the transistor offset voltage according to the third input signal.

公开(公告)号：US20190164498A1

公开(公告)日：2019-05-30

申请号：US16195220

申请日：2018-11-19

Applicant: LG Display Co., Ltd.

Inventor： YongHo JANG

IPC: G09G3/3266 ,  G09G3/32

Abstract: A gate driving circuit and a light emitting display apparatus including the same has a simplified circuit that outputs a stable emission control signal. The gate driving circuit includes an emission control shift register including a plurality of emission control stages that each respectively supply an emission control signal to one of a plurality of emission control lines, each emission control line connected to at least one pixel of a plurality of pixels in a light emitting display panel. For an emission control line, when at least one of first input signal and the second input signal has a first voltage level, an emission control stage outputs the emission control signal having a gate-off voltage level, and when both of the first input signal and the second input signal have a second voltage level, the corresponding emission control signal has a gate-on voltage level.

公开(公告)号：US20190130842A1

公开(公告)日：2019-05-02

申请号：US16176142

申请日：2018-10-31

Applicant: LG DISPLAY CO., LTD.

Inventor： YongHo JANG ,  WooSeok CHOI ,  KwangIl CHUN

IPC: G09G3/3266 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G2300/0814 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08

Abstract: According to an aspect of the present disclosure, a gate driver includes a plurality of stages which is dependently connected to each other and each of the plurality of pixels includes: a first output unit which outputs a sensing signal by voltages of a Q node and a QB node; a second output unit which outputs a reference signal by the voltages of the Q node and the QB node; a third output unit which outputs a scan signal by the voltages of the Q node and the QB node; a first controller which controls the Q node; and a second controller which controls the QB node, and at least two of the first to third output units share at least one clock signal among a plurality of clock signals, thereby reducing an area of the gate driver.

公开(公告)号：US20220208094A1

公开(公告)日：2022-06-30

申请号：US17469682

申请日：2021-09-08

Applicant: LG Display Co., Ltd.

Inventor： YongHo JANG ,  Younghyun KO

IPC: G09G3/3233 ,  G09G3/20 ,  H01L27/32

Abstract: The present specification provides a display device and a driving method thereof performing sampling for sensing a sampling voltage of a driving transistor using a fast mode in which a driving transistor operates by a sampling voltage formed in one storage capacitor, and data writing using the slow mode in which the driving transistor is operated by a data voltage formed in another storage capacitor.

公开(公告)号：US20180190824A1

公开(公告)日：2018-07-05

申请号：US15858679

申请日：2017-12-29

Applicant: LG Display Co., Ltd.

Inventor： JongUk BAE ,  YongHo JANG

IPC: H01L29/786 ,  H01L27/32 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: Disclosed are a thin film transistor, a method of manufacturing the same, and an organic light emitting display device including the same, in which a driving stability of a driving transistor is enhanced even without connecting a source electrode to a bottom gate electrode of the driving transistor. The film transistor includes a N-type semiconductor layer, a P-type semiconductor layer on the N-type semiconductor layer, a first gate electrode on the P-type semiconductor layer, a gate insulation layer between the first gate electrode and the P-type semiconductor layer, a first source electrode connected to a first side of the P-type semiconductor layer, and a first drain electrode connected to a second side of the P-type semiconductor layer.