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    Signal amplitude adjustment to improve resolver-to-digital converter performance
    1.
    发明授权
    Signal amplitude adjustment to improve resolver-to-digital converter performance 有权
    信号幅度调整，以提高分解器到数字转换器的性能

    公开(公告)号：US08274414B2

    公开(公告)日：2012-09-25

    申请号：US12635213

    申请日：2009-12-10

    申请人： Lalinda D. Fernando ,  Michael C. W. Coln

    发明人： Lalinda D. Fernando ,  Michael C. W. Coln

    IPC分类号： H03M1/48

    CPC分类号： G01B7/30

    摘要： An interface system between an RDC and a connected resolver dynamically matches an input range of the RDC to the output range of the resolver's output signals. The interface system may include methods and/or apparatuses to determine the amplitude of sinusoidal input signals presented to the RDC by the resolver and to compare the amplitude against high and low threshold values. A gain control signal may be generated, which may be corrected if the detected amplitude either exceeds the high threshold or falls below the low threshold. The gain control signal may be output to a circuit in the RDC or in the resolver that corrects any mismatch that occurs between the RDC input and the resolver output. For example, the gain control signal may control the amplitude of an excitation signal applied to a primary of the resolver or the gain control signal may be applied to an analog to digital converter at the input of the RDC to control its effective input range.

    摘要翻译： RDC和连接的解析器之间的接口系统动态地将RDC的输入范围与解算器的输出信号的输出范围进行匹配。 接口系统可以包括用于确定由解算器呈现给RDC的正弦输入信号的幅度并且将幅度与高和低阈值进行比较的方法和/或装置。 可以生成增益控制信号，如果检测到的幅度超过高阈值或低于低阈值，则可以校正增益控制信号。 增益控制信号可以被输出到RDC或解析器中的电路，该解算器校正RDC输入和解析器输出之间出现的任何失配。 例如，增益控制信号可以控制施加到旋转变压器的初级的激励信号的幅度，或者增益控制信号可以在RDC的输入端施加到模数转换器，以控制其有效输入范围。

    Serial digital data communication interface for transmitting data bits each having a width of multiple clock cycles
    3.
    发明授权
    Serial digital data communication interface for transmitting data bits each having a width of multiple clock cycles 有权
    串行数字数据通信接口，用于发送各自具有多个时钟周期宽度的数据位

    公开(公告)号：US08027421B2

    公开(公告)日：2011-09-27

    申请号：US11903529

    申请日：2007-09-21

    申请人： Michael C. W. Coln ,  Alain Guery

    发明人： Michael C. W. Coln ,  Alain Guery

    IPC分类号： H04L7/00

    CPC分类号： H04L7/10 ,  H04L7/0337 ,  H04L7/041 ,  H04L7/042 ,  H04L7/046

    摘要： A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

    摘要翻译： 用于从数据发射器12到数据接收器14的数据传输的串行协议和接口，其中传播延迟可以长达几个时钟周期并且可能缓慢变化。 数据接收器为数据发送器提供时钟。 由接收机或发射机提供的同步信号以由时钟控制的传输速率发起数据传输帧。 同步信号协调数据标题的传输，接着是预定数量的数据位，称为帧长度。 数据接收器使用标题位来确定对后续数据位采样的次数。 帧的长度被限制为提供传播延迟线特性没有足够变化以造成位错误的足够的可能性。 系统在每帧开始时重新同步。

    Sample and hold apparatus
    4.
    发明授权
    Sample and hold apparatus 有权
    采样和保持设备

    公开(公告)号：US07113116B2

    公开(公告)日：2006-09-26

    申请号：US11045672

    申请日：2005-01-26

    申请人： Robert J. Brewer ,  Colin G. Lyden ,  Michael C. W. Coln

    发明人： Robert J. Brewer ,  Colin G. Lyden ,  Michael C. W. Coln

    IPC分类号： H03M1/00

    CPC分类号： G11C27/026 ,  G11C27/024

    摘要： An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

    摘要翻译： 提供一种采集和平均电路，其中在采样相位期间，采样块4和6中的电容器顺序地连接到输入信号以对其进行采样，然后被隔离以保持样本。 然后将电容器连接到组合/平均布置，使得形成样本值的平均值。

    Accuracy of battery monitor parts
    5.
    发明授权
    Accuracy of battery monitor parts 有权
    电池监视器部件的精度

    公开(公告)号：US08515699B2

    公开(公告)日：2013-08-20

    申请号：US12613062

    申请日：2009-11-05

    申请人： Jeremy Richard Gorbold ,  Colin Charles Price ,  Michael C. W. Coln

    发明人： Jeremy Richard Gorbold ,  Colin Charles Price ,  Michael C. W. Coln

    IPC分类号： G01R31/36

    CPC分类号： G01R31/3658 ,  G01R35/005 ,  H01M10/425 ,  H01M10/482

    摘要： Embodiments of the present invention provide a monitoring system that may include a plurality of monitors. Each may have a plurality of input pairs coupled to respective components of a component stack, wherein adjacent monitors each have an input pair coupled to a common component. Embodiments of the present invention provide an integrated circuit that may include a plurality of detectors to locally measure a first group of channels. The integrated circuit may also include a receiver operable to receive a measurement of at least one channel of the first group of channels, and a controller to calculate a correction factor based on the received measurement and a local measurement of the at least one channel and to correct all first group measurements with the correction factor.

    摘要翻译： 本发明的实施例提供了一种可以包括多个监视器的监视系统。 每个可以具有耦合到部件堆叠的相应部件的多个输入对，其中相邻的监视器各自具有耦合到公共部件的输入对。 本发明的实施例提供一种集成电路，其可以包括多个检测器以局部地测量第一组信道。 集成电路还可以包括可操作以接收第一组信道的至少一个信道的测量的接收机，以及控制器，用于基于接收到的测量和至少一个信道的局部测量来计算校正因子，并且 使用校正因子校正所有第一组测量。

    Jitter and load insensitive charge transfer
    6.
    发明授权
    Jitter and load insensitive charge transfer 有权
    抖动和负载不敏感的电荷转移

    公开(公告)号：US06452531B1

    公开(公告)日：2002-09-17

    申请号：US09385211

    申请日：1999-08-27

    申请人： Gerald A. Miller ,  Michael C. W. Coln

    发明人： Gerald A. Miller ,  Michael C. W. Coln

    IPC分类号： H03M112

    CPC分类号： H03M3/464

    摘要： Methods and apparatus for jitter and load insensitive charge transfer are disclosed. A quantity of charge is transferred to or from a load during a transfer interval, wherein the charge transferred is significantly insensitive to load characteristics and variations in the transfer interval. A succession of identical or different quantities of charge may be transferred to or from the load during successive transfer intervals. The charge transfer circuit may be employed in mixed switched/continuous-time circuit configurations, and in particular may be used as a unipolar or bipolar one-bit digital-to-analog converter to provide quantized feedback in a sigma-delta analog-to-digital converter circuit configuration. The charge transfer circuit avoids problems of integrating amplifier nonlinearity and input signal distortion in such sigma-delta analog-to-digital converter circuits, and facilitates monolithic fabrication of sigma-delta analog-to-digital converters using standard integrated circuit fabrication techniques.

    摘要翻译： 公开了抖动和负载不敏感电荷转移的方法和装置。 在传送间隔期间，一定量的电荷被传送到负载，其中转移的电荷对负载特性和转移间隔的变化显着不敏感。 在连续的传送间隔期间，可以将相同或不同数量的电荷的连续传递到负载或从负载传送。 电荷转移电路可以用于混合开关/连续时间电路配置，并且特别地可以用作单极或双极的一位数模转换器，以在Σ-Δ模拟 - 数模转换器中提供量化反馈， 数字转换器电路配置。 电荷转移电路避免了在这种Σ-Δ模数转换器电路中集成放大器非线性和输入信号失真的问题，并且使用标准集成电路制造技术促进了Σ-Δ模数转换器的单片制造。

    Dual channel analog to digital converter
    8.
    发明授权
    Dual channel analog to digital converter 有权
    双通道模数转换器

    公开(公告)号：US06674386B2

    公开(公告)日：2004-01-06

    申请号：US10142500

    申请日：2002-05-10

    申请人： Gary R. Carreau ,  Bruce E. Amazeen ,  Michael C. W. Coln

    发明人： Gary R. Carreau ,  Bruce E. Amazeen ,  Michael C. W. Coln

    IPC分类号： H03M112

    CPC分类号： H03M1/1004 ,  H03M1/123

    摘要： A dual channel ADC uses two digital to analog converters (DACs) and a single comparator to convert two analog input channels. One DAC is used for successive approximation, while the other DAC is used for calibration. The dual channel ADC allows for sampling and conversion of single-ended, pseudo-differential, and fully differential analog input signals while maintaining layout symmetry and reducing crosstalk without substantially increasing circuit area. The single comparator is used for converting both analog input channels. Additional logic (such as switches or digital logic) is used to connect the input sampling capacitors and DACs to the appropriate inputs of the comparator for converting the analog input channels.

    摘要翻译： 双通道ADC使用两个数模转换器（DAC）和一个单个比较器来转换两个模拟输入通道。 一个DAC用于逐次逼近，而另一个DAC用于校准。 双通道ADC允许单端，伪差分和全差分模拟输入信号的采样和转换，同时保持布局对称性并减少串扰，而不会显着增加电路面积。 单个比较器用于转换两个模拟输入通道。 附加逻辑（如开关或数字逻辑）用于将输入采样电容和DAC连接到比较器的相应输入端，以转换模拟输入通道。

    Analog-to-digital converter with the ability to asynchronously sample signals without bias or reference voltage power consumption
    9.
    发明授权
    Analog-to-digital converter with the ability to asynchronously sample signals without bias or reference voltage power consumption 有权
    具有异步采样信号而无偏置或参考电压功耗的模数转换器

    公开(公告)号：US06667707B2

    公开(公告)日：2003-12-23

    申请号：US10136917

    申请日：2002-05-02

    申请人： Michael Mueck ,  Michael C. W. Coln

    发明人： Michael Mueck ,  Michael C. W. Coln

    IPC分类号： H03M112

    CPC分类号： H03M1/002 ,  H03K5/249 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/804

    摘要： A successive approximation routine analog-to-digital converter includes a switched-capacitor circuit that samples an input voltage into a plurality of capacitors without the need for power to be dissipated by the analog-to-digital converter. A comparator, coupled to the switched-capacitor circuit, compares a voltage across the capacitors with another voltage during each of a number of iterations. A common mode voltage of the switched-capacitor circuit is boosted during at least some of the iterations. The boost may be accomplished in many different ways and may be different for each of a single-ended, a quasi-differential and fully differential versions of the analog-to-digital converter.

    摘要翻译： 逐次逼近程序模数转换器包括开关电容器电路，其将输入电压采样到多个电容器中，而不需要由模数转换器消耗功率。 耦合到开关电容器电路的比较器在每次迭代期间将电容器两端的电压与另一电压进行比较。 在至少一些迭代期间，开关电容器电路的共模电压被升压。 升压可以以许多不同的方式实现，并且对于模数转换器的单端，准差分和全差分版本中的每一个可以是不同的。