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公开(公告)号：US08811068B1
公开(公告)日：2014-08-19
申请号：US13471353
申请日：2012-05-14
申请人： Lawrence T. Clark , Scott E. Thompson , Richard S. Roy , Robert Rogenmoser , Damodar R. Thummalapally
发明人： Lawrence T. Clark , Scott E. Thompson , Richard S. Roy , Robert Rogenmoser , Damodar R. Thummalapally
IPC分类号： G11C11/00
CPC分类号： G11C11/418 , G11C5/063 , G11C5/14 , G11C7/02 , G11C11/412 , G11C11/417 , G11C11/419 , H01L27/0207 , H01L27/1104 , H01L29/0649 , H01L29/1083 , H01L29/167 , H01L29/7833 , H01L29/7838
摘要： An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer. The screening region has a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer. The screening region can provide an enhanced body coefficient for the pull-up transistors to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. Related methods are also disclosed.
摘要翻译： 集成电路可以包括具有上拉晶体管，下拉晶体管和通过栅极晶体管的SRAM单元，其具有位于栅极下方的距离并且与半导体层分离的屏蔽区域。 筛选区域具有筛选区域掺杂剂的浓度，筛选区域掺杂剂的浓度高于半导体层中掺杂剂的浓度。 当偏置电压施加到屏蔽区域时，屏蔽区域可以为上拉晶体管提供增强的体系系数，以增加SRAM单元的读取静态噪声容限。 还公开了相关方法。
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2.发明申请公开(公告)号：US20130020638A1
公开(公告)日：2013-01-24
申请号：US13616053
申请日：2012-09-14
IPC分类号： H01L27/092
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
摘要翻译： 减少设备功耗的一些结构和方法可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免成本高昂的风险转换到替代技术。 一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT为 设置得更精确。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 本文提供的其他结构，配置和方法可以单独使用或与DDC结合使用，以产生额外和不同的益处。
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3.发明授权公开(公告)号：US08273617B2
公开(公告)日：2012-09-25
申请号：US12708497
申请日：2010-02-18
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.
摘要翻译： 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许具有掺杂剂的FET的阈值电压VT 要更精确地设置通道区域。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 配置DDC以实现不同的好处有许多方法，本文中提供的其他结构和方法可以单独使用或与DDC结合使用，以产生额外的好处。
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4.发明授权公开(公告)号：US08541824B2
公开(公告)日：2013-09-24
申请号：US13553593
申请日：2012-07-19
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
摘要翻译： 减少设备功耗的一些结构和方法可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免成本高昂的风险转换到替代技术。 一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的sigmaVT，并且可以允许在沟道区域中具有掺杂剂的FET的阈值电压VT被设置得很多 更确切地说。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 本文提供的其他结构，配置和方法可以单独使用或与DDC结合使用，以产生额外和不同的益处。
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公开(公告)号：US20130020639A1
公开(公告)日：2013-01-24
申请号：US13616859
申请日：2012-09-14
IPC分类号： H01L27/11
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
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6.发明授权公开(公告)号：US08604530B2
公开(公告)日：2013-12-10
申请号：US13616859
申请日：2012-09-14
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
摘要翻译： 减少设备功耗的一些结构和方法可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免成本高昂的风险转换到替代技术。 一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置为很多 更确切地说。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 本文提供的其他结构，配置和方法可以单独使用或与DDC结合使用，以产生额外和不同的益处。
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公开(公告)号：US08604527B2
公开(公告)日：2013-12-10
申请号：US13616053
申请日：2012-09-14
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
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8.发明申请公开(公告)号：US20110074498A1
公开(公告)日：2011-03-31
申请号：US12708497
申请日：2010-02-18
IPC分类号： G05F1/10 , H01L29/78 , H01L21/336 , H01L27/088 , H01L21/8236
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.
摘要翻译： 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许具有掺杂剂的FET的阈值电压VT 要更精确地设置通道区域。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 配置DDC以实现不同的好处有许多方法，本文中提供的其他结构和方法可以单独使用或与DDC结合使用，以产生额外的好处。
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9.发明申请公开(公告)号：US20120299111A1
公开(公告)日：2012-11-29
申请号：US13553593
申请日：2012-07-19
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/1083 , H01L21/0262 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L21/823493 , H01L21/823807 , H01L21/823892 , H01L21/84 , H01L27/0207 , H01L27/0921 , H01L27/11 , H01L27/1104 , H01L29/0653 , H01L29/105 , H01L29/1079 , H01L29/66545 , H01L29/66568 , H01L29/66628 , H01L29/7834 , H01L29/7838
摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
摘要翻译： 减少设备功耗的一些结构和方法可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免成本高昂的风险转换到替代技术。 一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT为 设置得更精确。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 本文提供的其他结构，配置和方法可以单独使用或与DDC结合使用，以产生额外和不同的益处。
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10.发明申请Junction field effect dynamic random access memory cell and content addressable memory cell 失效连接场效应动态随机存取存储单元和内容可寻址存储单元公开(公告)号：US20080285322A1
公开(公告)日：2008-11-20
申请号：US11804132
申请日：2007-05-17
IPC分类号： G11C15/04 , G11C15/00 , G11C11/24 , G11C11/34 , H01L27/105
CPC分类号： G11C15/043 , G11C11/405 , G11C2211/4068
摘要： A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs.
摘要翻译： 公开了一种包括动态随机存取存储器（DRAM）单元和三元内容寻址存储器（TCAM）单元的半导体存储器件。 DRAM单元可以包括数据存储部分和数据读取部分。 数据存储部分和数据读取部分包括p沟道结场效应晶体管。 TCAM单元包括x单元，y单元和比较器电路。 包括p沟道JFET的x单元，y单元和比较器电路。
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