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    HETEROGENEOUS COMPUTING SYSTEM COMPRISING A SWITCH/NETWORK ADAPTER PORT INTERFACE UTILIZING LOAD-REDUCED DUAL IN-LINE MEMORY MODULES (LR-DIMMS) INCORPORATING ISOLATION MEMORY BUFFERS
    1.
    发明申请
    HETEROGENEOUS COMPUTING SYSTEM COMPRISING A SWITCH/NETWORK ADAPTER PORT INTERFACE UTILIZING LOAD-REDUCED DUAL IN-LINE MEMORY MODULES (LR-DIMMS) INCORPORATING ISOLATION MEMORY BUFFERS 审中-公开
    包含开关/网络适配器端口接口的异构计算系统利用负载减少的双向在线存储器模块（LR-DIMMS）并入隔离存储器缓冲器

    公开(公告)号：US20120117318A1

    公开(公告)日：2012-05-10

    申请号：US13286996

    申请日：2011-11-01

    申请人： Lee A. Burton ,  Thomas R. Seeman ,  Jon M. Huppenthal

    发明人： Lee A. Burton ,  Thomas R. Seeman ,  Jon M. Huppenthal

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1663

    摘要： A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.

    摘要翻译： 异构计算系统包括利用负载减少的双列直插存储器模块（LR-DIMM）并入隔离存储器缓冲器的交换机/网络适配器端口接口。 在本发明的特定实施例中，计算机系统包括至少一个密集逻辑设备和将其耦合到存储器总线的控制器。 多个存储器插槽耦合到存储器总线，并且适配器端口与若干数量的多个存储器插槽相关联，每个适配器端口包括相关联的存储器资源。 直接执行逻辑元件耦合到至少一个适配器端口。 存储器资源可由至少一个密集逻辑器件和直接执行逻辑元件选择性地访问。

    Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
    2.
    发明授权
    Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers 有权
    交换机/网络适配器端口将可重配置处理元件耦合到一个或多个微处理器以与交错存储器控制器一起使用

    公开(公告)号：US07197575B2

    公开(公告)日：2007-03-27

    申请号：US10340390

    申请日：2003-01-10

    申请人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    发明人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    IPC分类号： G06F15/16

    CPC分类号： G06F13/1663 ,  G06F13/1684

    摘要： A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

    摘要翻译： 双串行内存模块（“DIMM”）或Rambus（TM）在线内存模块（“RIMM”）格式的交换机/网络适配器端口（“SNAP（TM）”），用于采用多自适应 处理器（“MAP（R）”，SRC Computers，Inc.的两个商标）用于交错存储器控制器的元件。 特别公开的是基于微处理器的计算机系统，其利用耦合到可重构处理器元件的DIMM或RIMM物理格式适配器端口来实现到外部交换机，网络或其他设备的连接。 在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。 基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。

    Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
    3.
    发明授权
    Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers 有权
    交换机/网络适配器端口将可重配置处理元件耦合到一个或多个微处理器以与交错存储器控制器一起使用

    公开(公告)号：US07565461B2

    公开(公告)日：2009-07-21

    申请号：US11203983

    申请日：2005-08-15

    申请人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    发明人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    IPC分类号： G06F3/00

    CPC分类号： G06F13/385 ,  G06F13/1652

    摘要： A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

    摘要翻译： 双串行内存模块（“DIMM”）或Rambus（TM）在线内存模块（“RIMM”）格式的交换机/网络适配器端口（“SNAP（TM）”），用于采用多自适应 处理器（“MAP（R）”，SRC Computers，Inc.的两个商标）用于交错存储器控制器的元件。 特别公开的是基于微处理器的计算机系统，其利用耦合到可重构处理器元件的DIMM或RIMM物理格式适配器端口来实现到外部交换机，网络或其他设备的连接。 在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。 基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。

    Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
    4.
    发明授权
    Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format 有权
    用于使用双列直插式存储器模块格式的多自适应处理器链的集群计算机的交换机/网络适配器端口

    公开(公告)号：US07373440B2

    公开(公告)日：2008-05-13

    申请号：US09932330

    申请日：2001-08-17

    申请人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    发明人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    IPC分类号： G06F13/12

    CPC分类号： G06F15/7867 ,  G06F13/4027

    摘要： A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

    摘要翻译： 在双列直插式存储器模块（“DIMM”）中使用采用多自适应处理器（“MAP”）（SRC Computers，Inc.的商标）的集群计算机的交换机/网络适配器端口（“SNAP” 或Rambus（TM）在线存储器模块（“RIMM”）格式，以显着增强通过使用标准外围组件互连（“PCI”）总线可获得的数据传输速率。 特别公开的是基于微处理器的计算机系统，其利用DIMM或RIMM物理格式处理器元件来实现与外部交换机，网络或其他设备的连接。 在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。 基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。

    Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
    6.
    发明授权
    Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format 有权

    公开(公告)号：US07421524B2

    公开(公告)日：2008-09-02

    申请号：US10996016

    申请日：2004-11-23

    申请人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    发明人： Jon M. Huppenthal ,  Thomas R. Seeman ,  Lee A. Burton

    IPC分类号： G06F13/12

    CPC分类号： G06F15/7867 ,  G06F13/4027

    摘要： A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

    Duty cycle control circuit and associated method
    8.
    发明授权
    Duty cycle control circuit and associated method 失效
    占空比控制电路及相关方法

    公开(公告)号：US5455530A

    公开(公告)日：1995-10-03

    申请号：US208946

    申请日：1994-03-09

    申请人： Jon M. Huppenthal ,  Lee A. Burton

    发明人： Jon M. Huppenthal ,  Lee A. Burton

    IPC分类号： H03K7/08 ,  H03K3/017

    CPC分类号： H03K7/08

    摘要： A duty cycle control circuit, and an associated method, generates an output clock signal having a duty cycle which differs by a desired amount with the duty cycle of an input clock signal. Offset bias signal circuitry generates an offset bias signal which offsets a copy clock signal and an inverted copy clock signal relative to one another by a selected offset bias. The duty cycle of the output clock signal differs with the duty cycle of the input clock signal by an amount which is related to the amplitude of the offset bias signal.

    摘要翻译： 占空比控制电路和相关联的方法产生具有与输入时钟信号的占空比相差期望量的占空比的输出时钟信号。 偏移偏置信号电路产生偏移偏置信号，该偏移偏置信号通过选择的偏移偏移相对于彼此偏移复制时钟信号和反相复制时钟信号。 输出时钟信号的占空比随着输入时钟信号的占空比与偏移偏置信号的幅度有关的量而不同。

    Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
    10.
    发明授权
    Reconfigurable processor module comprising hybrid stacked integrated circuit die elements 有权
    可重构处理器模块包括混合堆叠集成电路芯片元件

    公开(公告)号：US06627985B2

    公开(公告)日：2003-09-30

    申请号：US10012057

    申请日：2001-12-05

    申请人： Jon M. Huppenthal ,  D. James Guzy

    发明人： Jon M. Huppenthal ,  D. James Guzy

    IPC分类号： H01L2302

    CPC分类号： G06F15/7867 ,  H01L25/18 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

    摘要： A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

    摘要翻译： 一种可重构处理器模块，包括混合堆叠集成电路（“IC”）芯片元件。 在本文公开的特定实施例中，具有可重新配置能力的处理器模块可以通过堆叠一个或多个减薄的微处理器，存储器和/或现场可编程门阵列（“FPGA”）管芯元件并将其相互利用的触点互相连接， 死了 所公开的处理器模块允许在微处理器和FPGA元件之间共享数据的显着加速，同时有利地提高最终的组装产量并且同时降低最终组装成本。