公开(公告)号：US07585735B2

公开(公告)日：2009-09-08

申请号：US11047946

申请日：2005-02-01

申请人： Leo Mathew ,  Yang Du ,  Bich-Yen Nguyen ,  Voon-Yew Thean

发明人： Leo Mathew ,  Yang Du ,  Bich-Yen Nguyen ,  Voon-Yew Thean

IPC分类号： H01L21/8234

CPC分类号： H01L29/4983 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/7843

摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.

摘要翻译： 提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。 分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。 在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层， 或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。

公开(公告)号：US20060170016A1

公开(公告)日：2006-08-03

申请号：US11047946

申请日：2005-02-01

申请人： Leo Mathew ,  Yang Du ,  Bich-Yen Nguyen ,  Voon-Yew Thean

发明人： Leo Mathew ,  Yang Du ,  Bich-Yen Nguyen ,  Voon-Yew Thean

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/7843

摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.

摘要翻译： 提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。 分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。 在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层， 或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。

公开(公告)号：US07803670B2

公开(公告)日：2010-09-28

申请号：US11458902

申请日：2006-07-20

申请人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

发明人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

IPC分类号： H01L21/00

CPC分类号： H01L21/845 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

摘要翻译： 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。

公开(公告)号：US20080020515A1

公开(公告)日：2008-01-24

申请号：US11458902

申请日：2006-07-20

申请人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

发明人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

IPC分类号： H01L21/00

CPC分类号： H01L21/845 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

摘要翻译： 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。

公开(公告)号：US07781277B2

公开(公告)日：2010-08-24

申请号：US11383113

申请日：2006-05-12

申请人： Bich-Yen Nguyen ,  Voon-Yew Thean

发明人： Bich-Yen Nguyen ,  Voon-Yew Thean

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/0207 ,  H01L29/1033 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： An integrated circuit includes NMOS and PMOS transistors. The NMOS has a strained channel having first and second stress values along first and second axes respectively. The PMOS has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS and PMOS have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS may be less than the SA of the NMOS. The integrated circuit may include a tensile stressor of silicon nitride over the NMOS and a compressive stressor of silicon nitride over the PMOS.

摘要翻译： 集成电路包括NMOS和PMOS晶体管。 NMOS具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS具有沿第一和第二轴具有第三和第四应力值的应变通道。 第一值应力与第三值不同，第二值与第四值不同。 NMOS和PMOS具有公共长度（L）和有效宽度（W），但扩散长度（SA）和/或源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS可以包括位于栅极下方的有源层中的多个电介质结构。 PMOS的SA可以小于NMOS的SA。 集成电路可以包括氮化硅在NMOS上的拉伸应力源和在PMOS上的氮化硅的压应力。

公开(公告)号：US20070235807A1

公开(公告)日：2007-10-11

申请号：US11742955

申请日：2007-05-01

申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。

公开(公告)号：US20070218707A1

公开(公告)日：2007-09-20

申请号：US11375893

申请日：2006-03-15

申请人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean

发明人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean

IPC分类号： H01L21/31

CPC分类号： H01L21/32 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/84

摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.

摘要翻译： 形成电子器件的方法可以包括在覆盖在衬底上的半导体层上形成图案化的抗氧化层，并且图案化半导体层以形成半导体岛。 半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。 该方法还可以包括沿着半导体岛的一侧形成耐氧化材料或者沿半导体岛的一侧选择性地沉积半导体材料。 该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛， 并将抗氧化材料转化为含氧环境。

公开(公告)号：US07265004B2

公开(公告)日：2007-09-04

申请号：US11273092

申请日：2005-11-14

申请人： Voon-Yew Thean ,  Brian J. Goolsby ,  Linda B. McCormick ,  Bich-Yen Nguyen ,  Colita M. Parker ,  Mariam G. Sadaka ,  Victor H. Vartanian ,  Ted R. White ,  Melissa O. Zavala

发明人： Voon-Yew Thean ,  Brian J. Goolsby ,  Linda B. McCormick ,  Bich-Yen Nguyen ,  Colita M. Parker ,  Mariam G. Sadaka ,  Victor H. Vartanian ,  Ted R. White ,  Melissa O. Zavala

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/1203

摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

摘要翻译： 电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。 在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。 在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。 可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。 可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。 在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

公开(公告)号：US20070190745A1

公开(公告)日：2007-08-16

申请号：US11351518

申请日：2006-02-10

申请人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

发明人： Mariam Sadaka ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/823807 ,  H01L21/76264 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  Y10S438/973

摘要： A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

公开(公告)号：US07230264B2

公开(公告)日：2007-06-12

申请号：US11247866

申请日：2005-10-07

申请人： Voon-Yew Thean ,  Dina H. Triyoso ,  Bich-Yen Nguyen

发明人： Voon-Yew Thean ,  Dina H. Triyoso ,  Bich-Yen Nguyen

IPC分类号： H01L29/06

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

摘要： A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.

摘要翻译： 使用半导体衬底形成晶体管，并形成覆盖半导体衬底的控制电极。 第一电流电极形成在半导体衬底内并与控制电极相邻。 第一电流电极具有第一预定半导体材料。 第二电流电极形成在半导体衬底内并与控制电极相邻，以在半导体衬底内形成通道。 第二电流电极具有与第一预定半导体材料不同的第二预定半导体材料。 选择第一预定半导体材料以优化第一电流电极的带隙能量，并且选择第二预定半导体材料以优化通道的应变。