公开(公告)号：US20060024972A1

公开(公告)日：2006-02-02

申请号：US10901827

申请日：2004-07-29

申请人： Lindsey Hall ,  Trace Hurd ,  Deborah Riley

发明人： Lindsey Hall ,  Trace Hurd ,  Deborah Riley

IPC分类号： H01L21/302 ,  H01L21/311

CPC分类号： H01L21/31138 ,  G03F7/423 ,  G03F7/427 ,  H01L21/31133 ,  H01L21/8238 ,  H01L29/6659

摘要： The present invention provides a process of manufacturing a semiconductor device 200 while reducing silicon loss. In one aspect, the process includes removing a photoresist layer 270 from a semiconductor substrate 235 adjacent a gate 240 and cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layer 270 to a plasma ash. The plasma ash removes at least a portion of a crust 275 formed on the photoresist layer 270 but leaves a substantial portion of the photoresist layer 270. The photoresist layer 270 is subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer 270.

摘要翻译： 本发明提供一种在减少硅损耗的同时制造半导体器件200的工艺。 在一个方面，该方法包括从邻近门240的半导体衬底235去除光致抗蚀剂层270并用湿清洁溶液清洁半导体衬底。 去除步骤包括使光致抗蚀剂层270经受等离子体灰分。 等离子体灰去除形成在光致抗蚀剂层270上的外壳275的至少一部分，但留下光致抗蚀剂层270的大部分。 光致抗蚀剂层270在等离子体灰之后进行湿法蚀刻，其除去光致抗蚀剂层270的主要部分。

公开(公告)号：US20060035463A1

公开(公告)日：2006-02-16

申请号：US10914928

申请日：2004-08-10

申请人： Sue Crank ,  Shirin Siddiqui ,  Deborah Riley ,  Trace Hurd ,  Peijun Chen

发明人： Sue Crank ,  Shirin Siddiqui ,  Deborah Riley ,  Trace Hurd ,  Peijun Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/76829

摘要： A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non- thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

摘要翻译： 制备模具的方法包括在硅化物形成之前处理暴露的硅以形成氧化物; 并在氧化物上沉积金属。 金属可以在氧化物上包含钛，钴，镍，铂，钯，钨，钼或它们的组合。 氧化物可以小于或等于约15埃厚。 在各种实施方案中，处理暴露的硅以形成氧化物包括形成非热氧化物。 处理暴露的硅以形成氧化物还可以包括用氧化等离子体处理暴露的硅; 或者，处理暴露的硅以形成氧化物可包括形成化学氧化物。 在某些其他实施方案中，处理暴露的硅以形成氧化物包括用包含氢氧化铵，过氧化氢和水的溶液处理暴露的硅; 盐酸，过氧化氢和水; 过氧化氢; 臭氧; 臭氧化去离子水; 或其组合。

公开(公告)号：US20060115972A1

公开(公告)日：2006-06-01

申请号：US10999271

申请日：2004-11-29

申请人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

发明人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

IPC分类号： H01L21/4763 ,  H01L21/461

CPC分类号： H01L21/28088 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/6659

摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

摘要翻译： 本发明提供了一种图案化金属栅电极的方法和包括其的集成电路的制造方法。 除了其他步骤之外，用于图案化金属栅电极的方法包括在位于衬底（110）上的栅极电介质层（210）上形成金属栅极电极层（220），并且使用 干蚀刻工艺（410）和湿蚀刻工艺（510）的组合。

公开(公告)号：US20080020558A1

公开(公告)日：2008-01-24

申请号：US11861392

申请日：2007-09-26

申请人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

发明人： Antonio Rotondaro ,  Deborah Riley ,  Trace Hurd

IPC分类号： H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/4966 ,  H01L29/6659

摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

摘要翻译： 本发明提供了一种图案化金属栅电极的方法和包括其的集成电路的制造方法。 除了其他步骤之外，用于图案化金属栅电极的方法包括在位于衬底（110）上的栅极电介质层（210）上形成金属栅极电极层（220），并且使用 干蚀刻工艺（410）和湿蚀刻工艺（510）的组合。

公开(公告)号：US20060189066A1

公开(公告)日：2006-08-24

申请号：US11064583

申请日：2005-02-24

申请人： Brian Hornung ,  Jong Yoon ,  Deborah Riley ,  Amitava Chatterjee

发明人： Brian Hornung ,  Jong Yoon ,  Deborah Riley ,  Amitava Chatterjee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.

摘要翻译： 本发明在一个实施例中提供一种制造半导体器件（100）的方法。 在一个实施例中，该方法包括在第一掺杂剂区域122和第二掺杂剂区域128之上从衬底104,106生长氧化物层120，将第一掺杂剂注入到氧化物层120中，将第一掺杂剂注入第一掺杂剂区域 122，并且与栅极结构114相邻，并且在第二掺杂区128内基本上从衬底去除氧化物层120.在第二掺杂区128中去除氧化物层120之后，与第二掺杂区128相反的第二掺杂剂 第一掺杂剂注入到衬底106中并且在第二掺杂剂区128内并且与栅极结构114相邻。

公开(公告)号：US20060228904A1

公开(公告)日：2006-10-12

申请号：US11100530

申请日：2005-04-07

申请人： Deborah Riley ,  Brian Trentman ,  Brian Kirkpatrick

发明人： Deborah Riley ,  Brian Trentman ,  Brian Kirkpatrick

IPC分类号： H01L21/31

CPC分类号： H01L21/32139 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/28035 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76224

摘要： A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

摘要翻译： 提供了一种在湿蚀刻和剥离过程中保护暴露的硅免受磷酸侵蚀的方法。 根据该方法的各种实施例，可以在暴露的硅上形成厚的化学氧化物层，以保护暴露部分免受磷酸腐蚀。 该方法可以包括将硅暴露于热臭氧化硫酸和热过氧化硫酸中的至少一种以形成厚的化学氧化物。

公开(公告)号：US20140054710A1

公开(公告)日：2014-02-27

申请号：US13591976

申请日：2012-08-22

申请人： Youn Sung Choi ,  Deborah Riley ,  Shashank Sureshchandra Ekbote

发明人： Youn Sung Choi ,  Deborah Riley ,  Shashank Sureshchandra Ekbote

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each gate electrode. The SiGe structures overfill the recesses by at least about 30% of the depth of the recesses, as measured from the interface between the channel region and the overlying gate dielectric at the edge of the gate electrode. This overfill has been observed to reduce proximity effects of nearby shallow trench isolation structures on nearby transistors. Additional reduction in the proximity effect can be obtained by ensuring sufficient spacing between the edge of the gate electrode and a parallel edge of the nearest shallow trench isolation structure.

摘要翻译： 一种集成电路及其制造方法，利用嵌入的硅 - 锗（SiGe）源极/漏极区域，其中附近的浅沟槽隔离结构的邻近效应降低。 嵌入式SiGe源极/漏极结构通过选择性外延形成蚀刻到半导体表面中的每个栅电极的任一侧上的凹槽。 SiGe结构从沟槽区域和栅电极边缘处的上覆栅极电介质之间的界面测量到，凹槽的深度至少大约为凹槽深度的30％。 已经观察到这种过度填充以减少附近的晶体管附近的浅沟槽隔离结构的邻近效应。 可以通过确保栅电极的边缘与最近的浅沟槽隔离结构的平行边缘之间的足够间隔来获得邻近效应的附加减小。