摘要:
A method and apparatus for processing signals for display using a single frame buffer. In a preferred embodiment, a plurality of pixels are received, wherein one or more of the plurality of pixels corresponds to a first display and one or more of the plurality of pixels corresponds to a second display. A display bit map and a display mask are generated in accordance with the plurality of pixels. If a pixel of the plurality of pixels corresponds to the first display and a corresponding mask field of the display mask has a first-display value, then the pixel is stored in the display bit map, wherein the mask field comprises at least one mask bit. Otherwise, if the pixel corresponds to a key color, then the mask field corresponding to the pixel is set to the first-display value. Otherwise, the pixel is stored in the display bit map and the mask field corresponding to the pixel is set to a second-display value.
摘要:
A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.
摘要:
A device is provided that includes a first processor connected to a communications channel device. The communications device is capable of receiving and transmitting information to a video-on-demand (VOD) service provider. A VOD content decoder is provided that is conencted to the first processor. A video and audio formatting processor is provided that is connected to the first processor and the content decoder. An index memory is provided that is connected to the first processor. The index memory stores a plurality of VOD program segment representations of either whole VOD program content or partial VOD program content. Also provided is a method that includes selecting a start and stop time for recording a representation of a segment of at least one VOD program. The method also includes converting a VOD program identifier of at least one VOD program to a text representation. Also, either converting the text representation of the VOD program identifier of at least one VOD program into a unique encoded digital representation or receiving a unique encoded digital representation from the VOD service provider. Converting the start and stop time for a segment of at least one VOD program to a digital representation. And storing the VOD program identifier encoded digital representation and the start and stop digital representation in an index memory.
摘要:
A memory subsystem that includes a dynamic random-access memory (DRAM) having cells organized as an array of rows and columns, the cells being individually accessed by specifying a row address and a column address. An additional cell that stores a charge level is associated with each row of the DRAM. The charge level is characteristic of the charge level of the associated DRAM row, and is refreshed by a secondary or primary refresh cycle to the associated DRAM row. A threshold detector outputs a refresh signal when the charge of the additional cell drops below a predetermined threshold. Circuitry responsive to the refresh signal collects the row address of the additional cell and sends it to logic that generates a primary refresh cycle to the associated row address of the DRAM.
摘要:
A method and apparatus for translating a first address in a first address space, such as a processor address space, to a second address in a second address space, such as system address space, and for accessing a service routine in response to a page fault, are described. In one embodiment, the apparatus for translating comprises a processor; a page table having a translation mask register, a comparison value register, and a replacement value register; and a comparator coupled to the comparison value register and to the replacement value register. A programmable mask within the translation mask register is employed to partition a virtual address. A first subaddress comprises a subset of the bits of the first address and a second subaddress comprises remaining bits of the first address. The first subaddress is masked with a programmable mask value in the translation mask register and is compared by the comparator with successive values in the comparison value register until a match comparison value is found. If a match comparison value is found, a programmable replacement value in the replacement value register corresponding to the match comparison value is concatenated with the second subaddress to provide the second address. If a match comparison value is not found, a fault interrupt is generated to interrupt the translation and the processor accesses a service routine in accordance with the fault interrupt.
摘要:
An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.
摘要:
A request arbitration device is provided for prioritizing requests in a data processing system. A series of requests may arrive at the arbitration device at differing arrival times. The requests are accumulated to form a set of requests which is applied to a priority decode without any information on their relative arrival times. The priority device applies a fixed predetermined priority scheme to these requests. Simultaneously with the prioritizing of the first set of requests by the priority decode, a second set of requests may arrive at different arrival times. The requests of this second set of requests are likewise accumulated by the arbitration logic of a present invention. When arbitration of the first set of requests is complete, the second set of requests is then applied to the priority decode, again without any information with respect to their relative arrival times. The second set of requests is prioritized according to the same fixed predetermined priority scheme as the first set.
摘要:
The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.
摘要:
The reprogrammable RAM cartridge of the present invention is adapted for use as a reprogrammable video game. The cartridge uses an optoisolator connected in a circuit between the shield and ground lines to detect the presence of a signal indicating that the cartridge is in a programmer, rather than in a video game unit. While in the programmer, the program stored in the RAM can be changed. However, when removed from the programmer, the cartridge acts like a standard video game cartridge.
摘要:
An apparatus includes a decoder to receive a compressed bit stream that is based on a coding standard. The decoder includes a hardware accelerator to decode a part of the compressed bit stream that is based on an operation that is common across multiple coding standards that includes the coding standard. The decoder also includes a programmable element to decode a part of the compressed bit stream that is based on an operation that is specific to the coding standard.